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? 2013-2015 microchip technology inc. ds00001988a-page 1 highlights ? single-chip ethernet ph ysical layer transceiver (phy) ? compliant with energy efficient ethernet 802.3az ? comprehensive flexpwr technology - flexible power management architecture - lvcmos variable i/o voltage range: +1.8 v to +3.3 v - integrated 1.2 v regulator with disable feature ? hp auto-mdix support ? small footprint 32-pin vqfn, rohs-compliant package (5 x 5 x 0.9 mm height) ? deterministic 100 mb internal loopback latency (mii mode) target applications ? set-top boxes ? networked printers and servers ? test instrumentation ? lan on motherboard ? embedded telecom applications ? video record/playback systems ? cable modems/routers ? dsl modems/routers ? digital video recorders ? ip and video phones ? wireless access points ? digital televisions ? digital media adapters/servers ? gaming consoles ? poe applications (refer to microchip application note 17.18) key benefits ? high-performance 10/100 ethernet transceiver - compliant with ieee802. 3/802.3u (fast ethernet) - compliant with iso 802-3/ieee 802.3 (10base-t) - compliant with energy efficient ethernet ieee 802.3az - loop-back modes - auto-negotiation - automatic polarity de tection and correction - link status change wake-up detection - vendor specific register functions - supports both mii and the reduced pin count rmii interface ? power and i/os - various low power modes - integrated power-on reset circuit - two status led outputs - may be used with a single 3.3 v supply ? additional features - ability to use a low cost 25 mhz crystal for reduced bom ? packaging - 32-pin vqfn (5 x 5 mm), rohs-compliant package with mii and rmii ? environmental - commercial temperature range (0c to +70c) - industrial temperature range (-40c to +85c) lan8741a/lan8741ai small footprint mii/rmii 10/100 energy efficient ethernet transceiver with hp auto-mdix and flexpwr ? technology
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? 2013-2015 microchip technology inc. ds00001988a-page 3 lan8741a/lan8741ai table of contents 1.0 introduction .............................................................................................................. ....................................................................... 4 2.0 pin description and configuration ......................................................................................... ......................................................... 6 3.0 functional description .................................................................................................... .............................................................. 15 4.0 register descriptions ..................................................................................................... ............................................................... 44 5.0 operational charac teristics ............................................................................................... ............................................................ 83 6.0 package outline ........................................................................................................... ................................................................. 97 appendix a: revision history .................................................................................................. .......................................................... 100 the microchip web site ........................................................................................................ ............................................................ 103 customer change notification service .......................................................................................... ................................................... 103 customer support .............................................................................................................. ............................................................... 103 product identification system ................................................................................................. .......................................................... 104
lan8741a/lan8741ai ds00001988a-page 4 ? 2013-2015 microchip technology inc. 1.0 introduction 1.1 general terms and conventions the following is a list of the general terms used throughout this document: 1.2 general description the lan8741a/lan8741ai is a low-power 10base-t/100base-tx physical layer (phy) transceiver with variable i/o voltage that is compliant with the ieee 802.3, 802.3u, and 802.3az (energy efficient ethernet) standards. energy effi- cient ethernet (eee) support results in signif icant power savings during low link utilizations. the lan8741a/lan8741ai supports communication with an ethernet mac via a standard mii (ieee 802.3u)/rmii inter- face. it contains a full-duplex 10-base-t/100base-tx tran sceiver and supports 10 mbps (10base-t) and 100 mbps (100base-tx) operation. the lan8741a/l an8741ai implements auto-negotiation to automatically determine the best possible speed and duplex mode of operation. hp auto-mdix support allows the use of direct connect or cross-over lan cables. the lan8741a/lan8741ai s upports both ieee 802.3-2005 compliant and vendor-specific regi ster functions. however, no register access is required for operation. the initial co nfiguration may be selected vi a the configuration pins as described in section 3.7, "configuration straps" . register-selectable configuration options may be used to further define the functionality of the transceiver. per ieee 802.3-2005 standards , all digital interface pins are tolerant to 3.6 v. the device can be configur ed to operate on a single 3.3 v supply utilizing an int egrated 3.3 v to 1.2 v linear regulator. the linear regulator may be optionally disabled, allowing usage of a high efficiency external regulat or for lower system power dissipation. the lan8741a/lan8741ai is available in commercial (0c to +70c) and industrial (-40c to +85c) temperature range versions. a typical syst em application is shown in figure 1-1 . figure 1-2 provides an internal block diagram of the device. byte 8 bits fifo f irst i n f irst o ut buffer; often used for elasticity buffer mac m edia a ccess c ontroller mii m edia i ndependent i nterface rmii? r educed m edia i ndependent i nterface n/a not applicable x indicates that a logic state is ?don?t care? or undefined. reserved refers to a reserved bit field or address. unless otherwise noted, reserved bits must always be zero for write operations. unless otherwise noted, values are not guaranteed when reading reserved bits. unless otherwise noted, do not read or write to reserved addresses. smi s erial m anagement i nterface figure 1-1: system block diagram lan8741a/ lan8741ai 10/100 ethernet mac mii/ rmii mode led transformer crystal or clock oscillator mdi rj45
? 2013-2015 microchip technology inc. ds00001988a-page 5 lan8741a/lan8741ai figure 1-2: architectural overview rmii/mii logic interrupt generator leds pll receiver dsp system: clock data recovery equalizer squeltch & filters analog-to- digital 10m rx logic 100m rx logic 100m pll 10m pll transmitter 10m transmitter 100m transmitter 10m tx logic 100m tx logic central bias phy address latches lan8741a/lan8741ai rbias led1 nint xtal2 xtal1/clkin led2 management control mode control reset control mdix control hp auto-mdix rxp/rxn txp/txn txd[0:3] txen txer txclk rxd[0:3] rxdv rxer rxclk crs col/crs_dv mdc mdio auto- negotiation rmiisel nrst mode[0:2] smi phyad[0:2]
lan8741a/lan8741ai ds00001988a-page 6 ? 2013-2015 microchip technology inc. 2.0 pin description and configuration figure 2-1: 32-vqfn pin assignments (top view) note: when a lower case ?n? is used at the beginning of the sig nal name, it indicates that the signal is active low. for example, nrst indicates that the reset signal is active low. note: the buffer type for each signal is indicated in th e buffer type column. a descr iption of the buffer types is provided in section 2.2 . note: exposed pad (vss) on bottom of pa ckage must be conn ected to ground. mdio 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 rxd3/phyad2 rxclk/phyad1 vddcr xtal1/clkin xtal2 led1/regoff led2/nintsel vdd2a txd2 txd1 txd0 txen txclk nrst nint/txer/txd4 mdc txd3 rxdv vdd1a txn txp rxn rxp rbias col/crs_dv/mode2 crs rxer/rxd4/phyad0 vddio rxd0/mode0 rxd1/mode1 rxd2/rmiisel lan8741a/ lan8741ai
? 2013-2015 microchip technology inc. ds00001988a-page 7 lan8741a/lan8741ai table 2-1: mii/rmii signals num pins name symbol buffer type description 1 transmit data 0 txd0 vis the mac transmits data to the transceiver using this signal in all modes. 1 transmit data 1 txd1 vis the mac transmits data to the transceiver using this signal in all modes. 1 transmit data 2 (mii mode) txd2 vis the mac transmits data to the transceiver using this signal in mii mode. note: this signal must be grounded in rmii mode. 1 transmit data 3 (mii mode) txd3 vis the mac transmits data to the transceiver using this signal in mii mode. note: this signal must be grounded in rmii mode. 1 interrupt out- put nint vod8 (pu) active low interrupt output. place an external resis- tor pull-up to vddio. note: refer to section 3.6, "interrupt manage- ment" for additional details on device interrupts. note: refer to section 3.8.1.2, "nintsel and led2 polarity selection" for details on how the nintsel configuration strap is used to determine the function of this pin. transmit error (mii mode) txer vis when driven high, the 4b/5b encode process sub- stitutes the transmit error code-group (/h/) for the encoded data word. this input is ignored in the 10base-t mode of operation. this signal is also used in eee mode as txer when txen = 1, and as lpi when txen = 0. note: this signal is not used in rmii mode. transmit data 4 (mii mode) txd4 vis (pu) in symbol interface (5b decoding) mode, this sig- nal becomes the mii transmit data 4 line (the msb of the 5-bit symbol code-group). note: this signal is not used in rmii mode. 1 transmit enable txen vis (pd) indicates that valid transmission data is present on txd[3:0]. in rmii mode, only txd[1:0] provide valid data. 1 transmit clock (mii mode) txclk vo8 used to latch data from the mac into the trans- ceiver. ? mii (100base-tx): 25 mhz ? mii (10base-t): 2.5 mhz note: this signal is not used in rmii mode.
lan8741a/lan8741ai ds00001988a-page 8 ? 2013-2015 microchip technology inc. 1 receive data 0 rxd0 vo8 bit 0 of the 4 (2 in rmii mode) data bits that are sent by the transceiver on the receive path. phy operat- ing mode 0 configuration strap mode0 vis (pu) combined with mode1 and mode2 , this configu- ration strap sets the default phy mode. see note 1 for more information on configuration straps. note: refer to section 3.7.2, "mode[2:0]: mode configuration" for additional details. 1 receive data 1 rxd1 vo8 bit 1 of the 4 (2 in rmii mode) data bits that are sent by the transceiver on the receive path. phy operat- ing mode 1 configuration strap mode1 vis (pu) combined with mode0 and mode2 , this configu- ration strap sets the default phy mode. see note 1 for more information on configuration straps. note: refer to section 3.7.2, "mode[2:0]: mode configuration" for additional details. 1 receive data 2 (mii mode) rxd2 vo8 bit 2 of the 4 (in mii mode ) data bits that are sent by the transceiver on the receive path. note: this signal is not used in rmii mode. mii/rmii mode select configu- ration strap rmiisel vis (pd) this configuration strap selects the mii or rmii mode of operation. when strapped low to vss, mii mode is selected. when strapped high to vddio rmii mode is selected. see note 1 for more information on configuration straps. note: refer to section 3.7.3, "rmiisel: mii/rmii mode configuration" for addi- tional details. 1 receive data 3 (mii mode) rxd3 vo8 bit 3 of the 4 (in mii mode ) data bits that are sent by the transceiver on the receive path. note: this signal is not used in rmii mode. phy address 2 configuration strap phyad2 vis (pd) combined with phyad0 and phyad1 , this config- uration strap sets the transceiver?s smi address. see note 1 for more information on configuration straps. note: refer to section 3.7.1, "phyad[2:0]: phy address configuration" for addi- tional information. table 2-1: mii/rmii signals (continued) num pins name symbol buffer type description
? 2013-2015 microchip technology inc. ds00001988a-page 9 lan8741a/lan8741ai 1 receive error rxer vo8 this signal is asse rted to indicate that an error was detected somewhere in t he frame presently being transferred from the transceiver. this signal is also used in eee mode as rxer when rxdv = 1, and as lpi when rxdv = 0. note: this signal is optional in rmii mode. receive data 4 (mii mode) rxd4 vo8 in symbol interface (5b decoding) mode, this sig- nal is the mii receive data 4 signal, the msb of the received 5-bit symbol code-group. note: unless configured to the symbol inter- face mode, this pin functions as rxer. phy address 0 configuration strap phyad0 vis (pd) combined with phyad1 and phyad2 , this config- uration strap sets the transceiver?s smi address. see note 1 for more information on configuration straps. note: refer to section 3.7.1, "phyad[2:0]: phy address configuration" for addi- tional information. 1 receive clock (mii mode) rxclk vo8 in mii mode, this pin is the receive clock output. ? mii (100base-tx): 25 mhz ? mii (10base-t): 2.5 mhz phy address 1 configuration strap phyad1 vis (pd) combined with phyad0 and phyad2 , this config- uration strap sets the transceiver?s smi address. see note 1 for more information on configuration straps. note: refer to section 3.7.1, "phyad[2:0]: phy address configuration" for addi- tional information. 1 receive data valid rxdv vo8 indicates that recove red and decoded data is avail- able on the rxd pins. 1 collision detect (mii mode) col vo8 this signal is asserted to indicate detection of a collision condition in mii mode. carrier sense / receive data valid (rmii mode) crs_dv vo8 this signal is asserted to indicate the receive medium is non-idle in rmii mode. when a 10base-t packet is received, crs_dv is asserted, but rxd[1:0] is held low until the sfd byte (10101011) is received. note: per the rmii standard, transmitted data is not looped back onto the receive data pins in 10base-t half-duplex mode. phy operat- ing mode 2 configuration strap mode2 vis (pu) combined with mode0 and mode1 , this configu- ration strap sets the default phy mode. see note 1 for more information on configuration straps. note: refer to section 3.7.2, "mode[2:0]: mode configuration" for additional details. table 2-1: mii/rmii signals (continued) num pins name symbol buffer type description
lan8741a/lan8741ai ds00001988a-page 10 ? 2013-2015 microchip technology inc. note 1: configuration strap values are latc hed on power-on reset and system rese t. configuration straps are iden- tified by an underlined symbol name. signals that functi on as configuration straps must be augmented with an external resistor when connected to a load. refer to section 3.7, "configuration straps" for additional information. 1 carrier sense (mii mode) crs vo8 (pd) this signal indicates detection of a carrier in mii mode. table 2-2: led pins num pins name symbol buffer type description 1 led 1 led1 o12 link activity led indication. this pin is driven active when a valid link is detected and blinks when activ- ity is detected. note: refer to section 3.8.1, "leds" for addi- tional led information. regulator off configuration strap regoff is (pd) this configuration strap is used to disable the inter- nal 1.2 v regulator. when the regulator is disabled, external 1.2 v must be supplied to vddcr. ? when regoff is pulled high to vdd2a with an external resistor, the internal regulator is disabled. ? when regoff is floating or pulled low, the internal regulator is enabled (default). see note 1 for more information on configuration straps. note: refer to section 3.7.4, "regoff: inter- nal +1.2 v regulator configuration" for additional details. 1 led 2 led2 o12 link speed led indication. this pin is driven active when the operating speed is 100 mbps. it is inactive when the operating speed is 10 mbps or during line isolation. note: refer to section 3.8.1, "leds" for addi- tional led information. nint/txer/ txd4 function select configu- ration strap nintsel is (pu) this configuration strap selects the mode of the nint/txer/txd4 pin. ? when nintsel is floated or pulled to vdd2a, nint is selected for operation on the nint/txer/txd4 pin (default). ? when nintsel is pulled low to vss, txer/txd4 is selected for operation on the nint/txer/txd4 pin. see note 1 for more information on configuration straps. note: refer to see section 3.8.1.2, "nintsel and led2 polarity selection" for addi- tional information. table 2-1: mii/rmii signals (continued) num pins name symbol buffer type description
? 2013-2015 microchip technology inc. ds00001988a-page 11 lan8741a/lan8741ai note 1: configuration strap values are latc hed on power-on reset and system rese t. configuration straps are iden- tified by an underlined symbol name. signals that functi on as configuration straps must be augmented with an external resistor when connected to a load. refer to section 3.7, "configuration straps" for additional information. table 2-3: serial management interface (smi) pins num pins name symbol buffer type description 1smi data input/output mdio vis/ vo8 (pu) serial management interface data input/output 1 smi clock mdc vis serial management interface clock table 2-4: ethernet pins num pins name symbol buffer type description 1 ethernet tx/rx posi- tive channel 1 txp aio transmit/receive positive channel 1 1 ethernet tx/rx nega- tive channel 1 txn aio transmit/receive negative channel 1 1 ethernet tx/rx posi- tive channel 2 rxp aio transmit/receive positive channel 2 1 ethernet tx/rx nega- tive channel 2 rxn aio transmit/receive negative channel 2 table 2-5: miscellaneous pins num pins name symbol buffer type description 1 external crystal input xtal1 iclk external crystal input external clock input clkin iclk single-ended clock oscillator input. note: when using a single ended clock oscillator, xtal2 should be left uncon- nected. 1 external crystal out- put xtal2 oclk external crystal output 1 external reset nrst vis (pu) system reset. this signal is active low.
lan8741a/lan8741ai ds00001988a-page 12 ? 2013-2015 microchip technology inc. table 2-6: analog reference pins num pins name symbol buffer type description 1 external 1% bias resistor input rbias ai this pin requires connection of a 12.1 k ? (1%) resistor to ground. refer to the lan8741a/lan8741ai reference schematic for connection information. note: the nominal voltage is 1.2 v and the resistor will dissipate approximately 1 mw of power. table 2-7: power pins num pins name symbol buffer type description 1 +1.8 v to +3.3 v variable i/o power vddio p +1.8 v to +3.3 v variable i/o power. refer to the lan8741a/lan8741ai reference schematic for connection information. 1 +1.2 v digital core power supply vddcr p supplied by the on-chip regulator unless config- ured for regulator off mode via the regoff con- figuration strap. refer to the lan8741a/lan8741ai reference schematic for connection information. note: 1 f and 470 pf decoupling capaci- tors in parallel to ground should be used on this pin. 1 +3.3 v channel 1 analog port power vdd1a p +3.3 v analog port power to channel 1. refer to the lan8741a/lan8741ai reference schematic for connection information. 1 +3.3 v channel 2 analog port power vdd2a p +3.3 v analog port power to channel 2 and the internal regulator. refer to the lan8741a/lan8741ai reference schematic for connection information. 1 ground vss p common ground. this exposed pad must be con- nected to the ground plane with a via array.
? 2013-2015 microchip technology inc. ds00001988a-page 13 lan8741a/lan8741ai 2.1 pin assignments table 2-8: 32-vqfn package pin assignments pin num pin name pin num pin name 1 vdd2a 17 mdc 2 led2/nintsel 18 nint/txer/txd4 3led1/regoff 19 nrst 4xtal220 txclk 5 xtal1/clkin 21 txen 6 vddcr 22 txd0 7 rxclk/phyad1 23 txd1 8 rxd3/phyad2 24 txd2 9 rxd2/rmiisel 25 txd3 10 rxd1/mode1 26 rxdv 11 rxd0/mode0 27 vdd1a 12 vddio 28 txn 13 rxer/rxd4/phyad0 29 txp 14 crs 30 rxn 15 col/crs_dv/mode2 31 rxp 16 mdio 32 rbias
lan8741a/lan8741ai ds00001988a-page 14 ? 2013-2015 microchip technology inc. 2.2 buffer types table 2-9: buffer types buffer type description is schmitt-triggered input o12 output with 12 ma sink and 12 ma source vis variable voltage schmitt-triggered input vo8 variable voltage output with 8 ma sink and 8 ma source vod8 variable voltage open-drain output with 8 ma sink pu 50 a (typical) internal pull-up. unless otherwis e noted in the pin description, internal pull-ups are always enabled. note: internal pull-up resistors prevent unconnec ted inputs from floating. do not rely on internal resistors to drive signals external to the device. when connected to a load that must be pulled high, an external resistor must be added. pd 50 a (typical) internal pull-down. unless other wise noted in the pin description, internal pull- downs are always enabled. note: internal pull-down resistors prevent unconn ected inputs from floating. do not rely on internal resistors to drive signals exte rnal to the device. when connected to a load that must be pulled low, an external resistor must be added. ai analog input aio analog bi-directional iclk crystal oscillator input pin oclk crystal oscillator output pin p power pin note: the digital signals are not 5 v tolerant. refer to section 5.1, "absolute maximum ratings*" for additional buffer information. note: sink and source capabilities are dependent on the vddio voltage. refer to section 5.1, "absolute maxi- mum ratings*" for additional information.
? 2013-2015 microchip technology inc. ds00001988a-page 15 lan8741a/lan8741ai 3.0 functional description this chapter provides functional descr iptions of the various device features . these features have been categorized into the following sections: ? transceiver ? auto-negotiation ? hp auto-mdix support ? mac interface ? serial management interface (smi) ? interrupt management ? configuration straps ? miscellaneous functions ? application diagrams 3.1 transceiver 3.1.1 100base-tx transmit the 100base-tx transmit data path is shown in figure 3-1 . each major block is explained in the following subsections. 3.1.1.1 100base-tx transm it data across the mii/rmii interface for mii, the mac controller drives the transmit data onto the txd bus and asserts txen to indicate valid data. the data is latched by the transceiver?s mii block on the rising edge of txclk. the data is in the form of 4-bit wide 25 mhz data. for rmii, the mac controller dr ives the transmit data onto the txd bus and asserts txen to indicate valid data. the data is latched by the transceiver?s rmii block on the rising edge of ref_clk. the data is in the form of 2-bit wide 50 mhz data. 3.1.1.2 4b/5b encoding the transmit data passes from the mii/rmii block to the 4b/5b encoder. this block encodes the data from 4-bit nibbles to 5-bit symbols (known as ?code-groups?) according to table 3-1 . each 4-bit data-nibble is mapped to 16 of the 32 pos- sible code-groups. the remaining 16 code-groups are ei ther used for control information or are not valid. the first 16 code-groups are referred to by the hexadecimal va lues of their corresponding data nibbles, 0 through f. the remaining code-groups are given letter designations with slas hes on either side. for example, an idle code-group is /i/, a transmit error co de-group is /h/, etc. figure 3-1: 100base-tx transmit data path mac tx driver mlt-3 converter nrzi converter 4b/5b encoder cat-5 rj45 25 mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 scrambler and piso mii/rmii 25 mhz by 4 bits ext ref_clk (for rmii only) pll mii 25 mhz by 4 bits or rmii 50 mhz by 2 bits mlt-3 magnetics 125 mbps serial tx_clk (for mii only)
lan8741a/lan8741ai ds00001988a-page 16 ? 2013-2015 microchip technology inc. table 3-1: 4b/5b code table code group sym receiver interpretation transmitter interpretation 11110 0 0 0000 data 0 0000 data 01001 1 1 0001 1 0001 10100 2 2 0010 2 0010 10101 3 3 0011 3 0011 01010 4 4 0100 4 0100 01011 5 5 0101 5 0101 01110 6 6 0110 6 0110 01111 7 7 0111 7 0111 10010 8 8 1000 8 1000 10011 9 9 1001 9 1001 10110 a a 1010 a 1010 10111 b b 1011 b 1011 11010 c c 1100 c 1100 11011 d d 1101 d 1101 11100 e e 1110 e 1110 11101 f f 1111 f 1111 11111 i idle sent after /t/r until txen 11000 j first nibble of ssd, translated to ?0101? following idle, else rxer sent for rising txen 10001 k second nibble of ssd, translated to ?0101? following j, else rxer sent for rising txen 01101 t first nibble of esd, causes de-assertion of crs if followed by /r/, else assertion of rxer sent for falling txen 00111 r second nibble of esd, causes deasser- tion of crs if following /t/, else assertion of rxer sent for falling txen 00100 h transmit error symbol sent for rising txer 00110 v invalid, rxer if during rxdv invalid 11001 v invalid, rxer if during rxdv invalid 00000 v indicates to receiver that the transmitter will be going to lpi sent due to lpi. used to tell receiver before transmitter goes to lpi. also used for refresh cycles during lpi. 00001 v invalid, rxer if during rxdv invalid 00010 v invalid, rxer if during rxdv invalid 00011 v invalid, rxer if during rxdv invalid 00101 v invalid, rxer if during rxdv invalid 01000 v invalid, rxer if during rxdv invalid 01100 v invalid, rxer if during rxdv invalid 10000 v invalid, rxer if during rxdv invalid
? 2013-2015 microchip technology inc. ds00001988a-page 17 lan8741a/lan8741ai 3.1.1.3 scrambling repeated data patterns (especially the idle code-group) ca n have power spectral densities with large narrow-band peaks. scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. this uniform spectral density is requir ed by fcc regulations to prevent excessive emi from being radiated by the physical wiring. the seed for the scrambler is gener ated from the transceiver address, phyad , ensuring that in multiple-transceiver applications, such as repeaters or switches, each transceiver will have its own scrambler sequence. the scrambler also performs the parallel in serial out conversion (piso) of the data. 3.1.1.4 nrzi and mlt-3 encoding the scrambler block passes the 5-bit wide parallel data to the nrzi converter where it becomes a serial 125 mhz nrzi data stream. the nrzi is encoded to mlt-3. mlt-3 is a tri- level code where a change in the logic level represents a code bit ?1? and the logic output remaining at the same level represents a code bit ?0?. 3.1.1.5 100m transmit driver the mlt3 data is then passed to the analog transmitter, whic h drives the differential mlt-3 signal, on outputs txp and txn, to the twisted pair media across a 1:1 ratio isol ation transformer. the 10base-t and 100base-tx signals pass through the same transformer so that common ?magnetics? c an be used for both. the transm itter drives into the 100 ? impedance of the cat-5 cable. cable termination a nd impedance matching require external components. 3.1.1.6 100m phase lock loop (pll) the 100m pll locks onto reference clock and generates t he 125 mhz clock used to drive the 125 mhz logic and the 100base-tx transmitter. 3.1.2 100base-tx receive the 100base-tx receive da ta path is shown in figure 3-2 . each major block is explained in the following subsections. figure 3-2: 100base-tx receive data path mac a/d converter mlt-3 converter nrzi converter 4b/5b decoder magnetics cat-5 rj45 pll mii 25 mhz by 4 bits or rmii 50 mhz by 2 bits rx_clk (for mii only) 25 mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 6 bit data descrambler and sipo 125 mbps serial dsp: timing recovery, equalizer and blw correction mlt-3 mii/rmii 25 mhz by 4 bits ext ref_clk (for rmii only)
lan8741a/lan8741ai ds00001988a-page 18 ? 2013-2015 microchip technology inc. 3.1.2.1 100m receive input the mlt-3 from the cable is fed into the transceiver (on inputs rxp and rxn) via a 1:1 ratio transformer. the adc samples the incoming differential signal at a rate of 125m samples per second. using a 64-level quanitizer, it generates 6 digital bits to represent each sample. the dsp adjusts the gain of the adc according to the observed signal levels such that the full dynamic range of the adc can be used. 3.1.2.2 equalizer, baseline wander correction and clock and data recovery the 6 bits from the adc are fed into the dsp block. the equ alizer in the dsp section compensates for phase and ampli- tude distortion caused by the physical channel consisting of magnetics, connectors, and cat- 5 cable. the equalizer can restore the signal for any good-quality cat-5 cable between 1 m and 100 m. if the dc content of t he signal is such that the low-frequency comp onents fall below the low frequency pole of the iso- lation transformer, then the droop characteristics of the transformer will become significant and baseline wander (blw) on the received signal will result. to prevent corruption of the received data, the transceiver corrects for blw and can receive the ansi x3.263-1995 fddi tp-pmd defined ?killer packet? with no bit errors. the 100m pll generates multiple phases of the 125 mhz clock. a multiplexer, controlled by the timing unit of the dsp, selects the optimum phase for sampling the data. this is used as the received recovered clock. this clock is used to extract the serial data from the received signal. 3.1.2.3 nrzi and mlt-3 decoding the dsp generates the mlt-3 recovered le vels that are fed to the mlt-3 converter. the mlt-3 is then converted to an nrzi data stream. 3.1.2.4 descrambling the descrambler performs an inverse function to the scrambler in the transmitter and also performs the serial in parallel out (sipo) conversion of the data. during reception of idle (/i/) symbols. the descrambler synchronizes its descram bler key to the incoming stream. once synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data. special logic in the descrambler ensures synchronization wi th the remote transceiver by searching for idle symbols within a window of 4000 bytes (40 s). this window ensures th at a maximum packet size of 1514 bytes, allowed by the ieee 802.3 standard, can be received wi th no interference. if no idle-symbols are detected within this time-period, receive operation is aborted and the descram bler re-starts the synchronization process. 3.1.2.5 alignment the de-scrambled signal is then aligned into 5-bit code-grou ps by recognizing the /j/k/ st art-of-stream delimiter (ssd) pair at the start of a packet. once the code-word alignment is determined, it is stored and utilized until the next start of frame. 3.1.2.6 5b/4b decoding the 5-bit code-groups are translated into 4-bit data nibble s according to the 4b/5b table. the translated data is pre- sented on the rxd[3:0] signal lines. the ssd, /j/k/, is translated to ?0101 0101? as the first 2 nibbles of the mac pre- amble. reception of the ssd ca uses the transceiver to assert the receive da ta valid signal, indicating that valid data is available on the rxd bus. successive valid code-groups are tr anslated to data nibbles. reception of either the end of stream delimiter (esd) consisting of the /t/r/ symbols, or at least two /i/ symb ols causes the transceiver to de-assert the carrier sense and receive data valid signals. note: these symbols are not translated into data.
? 2013-2015 microchip technology inc. ds00001988a-page 19 lan8741a/lan8741ai 3.1.2.7 receive data valid signal the receive data valid signal (rxdv) indicates that recovered and decoded nibbles are being presented on the rxd[3:0] outputs synchronous to rxclk. rxdv becomes active after the /j/k / delimiter has been recognized and rxd is aligned to nibble boundaries. it remains active until either the /t/r/ delimiter is recognized or link test indicates failur e or sigdet becomes false. rxdv is asserted when the first nibble of translated /j/k/ is ready for transfe r over the media independent interface (mii mode). 3.1.2.8 receiver errors during a frame, unexpected code-groups are considered re ceive errors. expected code groups are the data set (0 through f), and the /t/r/ (esd) symbol pair. when a receive error occurs, the rxer signal is asserted and arbitrary data is driven onto the rxd[3:0] lines. should an error be detected during the time that the /j/k/ delimiter is being decoded (bad ssd error), rxer is asserted true and the value ?1110? is driven onto the rxd[3:0] lines. note that the valid data signal is not yet asserted when the bad ssd error occurs. 3.1.2.9 100m receive data across the mii/rmii interface in mii mode, the 4-bit data nibbles are sent to the mii block. these data nibbles are clocked to the controller at a rate of 25 mhz. the controller samples the data on the rising edge of rxclk. to ensure that the setup and hold require- ments are met, the nibbles are clocked out of the transcei ver on the falling edge of rxclk. rxclk is the 25 mhz output clock for the mii bus. it is recovered from the received data to clock the rxd bus. if there is no received signal, it is derived from the system reference clock (xtal1/clkin). when tracking the received data, rxclk has a maximum jitter of 0.8 ns (provided that th e jitter of the input clock, xtal1/clkin, is below 100 ps). in rmii mode, the 2-bit data nibbles are sent to the rmii block. these data nibbles are clocked to the controller at a rate of 50 mhz. the controller samples the da ta on the rising edge of xtal1/clkin (ref_clk). to ensure that the setup and hold requirements are met, the nibbles are clocked ou t of the transceiver on the falling edge of xtal1/clkin (ref_clk). 3.1.3 10base-t transmit data to be transmitted comes from the mac layer controller . the 10base-t transmitter receiv es 4-bit nibbl es from the mii at a rate of 2.5 mhz and converts them to a 10 mbps serial data stream. the dat a stream is t hen manchester- encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics. the 10m transmitter uses the following blocks: ? mii (digital) ? tx 10m (digital) ? 10m transmitter (analog) ? 10m pll (analog) figure 3-3: relationship between received data and specific mii signals 5d 5 data data data data rxd rx_dv rx_clk 5d 5 data data data data clear-text 5 jk 5 55 tr idle
lan8741a/lan8741ai ds00001988a-page 20 ? 2013-2015 microchip technology inc. 3.1.3.1 10m transmit data across the mii/rmii interface the mac controller drives the transmit data onto the txd bus. for mii, when the controller has driven txen high to indicate valid data, the data is latched by the mii block on the rising edge of txclk. the data is in the form of 4-bit wide 2.5 mhz data. for rmii, txd[1:0] shall transition synchron ously with respect to ref_clk. when txen is asserted, txd[1:0] are accepted for transmission by the device. txd[1:0] shall be ?00? to indicate idle when txen is deasserted. values of txd[1:0] other than ?00? when txen is deasserted are reserved for out-of-band signaling (to be defined). values other than ?00? on txd[1:0] while txen is deasserted shall be ignored by the device.txd[1:0] shall provide valid data for each ref_clk period while txen is asserted. in order to comply with legacy 10base-t mac/controllers, in half-duplex mode the transceiver loops back the trans- mitted data, on the receive path. this does not confuse the mac/controller since the col signal is not asserted during this time. the transceiver also supports the sqe (heartbeat) signal. see section 3.8.8, "collision detect" , for more details. 3.1.3.2 manchester encoding the 4-bit wide data is sent to the 10m tx block. the nibbles are converted to a 10 mbps serial nrzi data stream. the 10m pll locks onto the external clock or internal oscillator and produces a 20 mhz clock. this is used to manchester encode the nrz data stream. when no data is being transmitted (txen is low), the 10m tx block outputs normal link pulses (nlps) to maintain communications with the remote link partner. 3.1.3.3 10m transmit drivers the manchester-encoded data is sent to the analog transmitter where it is s haped and filtered bef ore being driven out as a differential signal acro ss the txp and txn outputs. 3.1.4 10base-t receive the 10base-t receiver gets the manchester- encoded analog sign al from the cable via the magnetics. it recovers the receive clock from the signal and uses this clock to recover the nrzi data stream. this 10m serial data is converted to 4-bit data nibbles which are passed to the co ntroller via mii at a rate of 2.5 mhz. this 10m receiver uses the following blocks: ? filter and squelch (analog) ? 10m pll (analog) ? rx 10m (digital) ? mii (digital) 3.1.4.1 10m receive input and squelch the manchester signal from the cable is fed into the transceiver (on inputs r xp and rxn) via 1:1 ratio magnetics. it is first filtered to reduce any out-of-ban d noise. it then passes through a squelch circuit. the squelch is a set of amplitude and timing comparators that normally reject differ ential voltage levels below 300 mv and detect and recognize differential voltages above 585 mv. 3.1.4.2 manchester decoding the output of the squelch goes to the 10m rx block where it is validated as manchester encoded data. the polarity of the signal is also checked. if the pol arity is reversed (local rxp is connect ed to rxn of the remote partner and vice versa), the condition is identified and corrected. the reversed condition is indicated by the xpol bit of the special con- trol/status indi cations register . the 10m pll is locked onto the received m anchester signal, from which the 20 mhz cock is generated. using this clock, the manchester encode d data is extracted and converted to a 10 mhz nrzi data stream. it is then converted from serial to 4-bit wide parallel data. the 10m rx block also detects valid 10 base-t idle signals - normal link puls es (nlps) - to ma intain the link.
? 2013-2015 microchip technology inc. ds00001988a-page 21 lan8741a/lan8741ai 3.1.4.3 10m receive data acro ss the mii/rmii interface for mii, the 4-bit data nibbles are sent to the mii block. in mii mode, these data nibbles are valid on the rising edge of the 2.5 mhz rxclk. for rmii, the 2-bit data nibbles are sent to the rmii block. in rmii mode, these data nibbles are valid on the rising edge of the rmii ref_clk. 3.1.4.4 jabber detection jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition, which results in holding the txen input for a long period. special logic is used to detect the jabber state and abort the transmission to the line within 45 ms. once txen is deasserted, the logic resets the jabber condition. as shown in section 4.2.2, "basic status register" , the jabber detect bit indicates that a jabber condition was detected. 3.2 auto-negotiation the purpose of the auto-ne gotiation function is to automat ically configure the transceiver to the optimum link parameters based on the capabilities of its link pa rtner. auto-negotiation is a mechanism fo r exchanging configuration information between two link-partners and automatic ally selecting the highest performance mode of operation supported by both sides. auto-negotiation is fully defined in clause 28 of the ieee 802.3 specification. once auto-negotiation has completed, information about the resolved link can be passed back to the controller via the serial management interface (smi ). the results of the negotiation process are reflected in the speed indication bits of the phy special control/status register , as well as in the auto negotiation link partner ability register . the auto-nego- tiation protocol is a purely physical layer activi ty and proceeds independent ly of the mac controller. the advertised capabilities of t he transceiver are stored in the auto negotiation advertisement register . the default advertised by the transceiver is determined by user-defined on-chip signal options. the following blocks are activated during an auto-negotiation session: ? auto-negotiation (digital) ? 100m adc (analog) ? 100m pll (analog) ? 100m equalizer/blw/clock recovery (dsp) ? 10m squelch (analog) ? 10m pll (analog) ? 10m transmitter (analog) when enabled, auto-negotiation is started by the occurrence of one of the following events: ? hardware reset ? software reset ? power-down reset ? link status down ? setting the restart auto-negotiate bit of the basic control register on detection of one of these events, the transceiver begins auto-negotiation by transmitting bursts of fast link pulses (flp), which are bursts of link pulses from the 10m transmitter. they are shaped as normal link pulses and can pass uncorrupted down cat-3 or cat-5 cable. a fast link pulse burst consists of up to 33 pulses. the 17 odd-numbered pulses, which are always present, frame the flp burst. the 16 even-numbered pu lses, which may be present or absent, contain the data word being transmitted. presence of a dat a pulse represents a ?1?, while absence represents a ?0?. the data transmitted by an flp burst is known as a ?link code word.? these are defined fully in ieee 802.3 clause 28. in summary, the transceiver advertises 802.3 compliance in its se lector field (the first 5 bits of the link code word). it advertises its technology ability a ccording to the bits set in the auto negotiation advertisement register . note: rxdv goes high with the sfd.
lan8741a/lan8741ai ds00001988a-page 22 ? 2013-2015 microchip technology inc. there are 4 possible matches of the technology abilities. in the order of priority these are: ? 100m full duplex (highest priority) ? 100m half duplex ? 10m full duplex ? 10m half duplex (lowest priority) if the full capabilities of the transceiver are advertised (100 m, full duplex), and if the link partner is capable of 10m and 100m, then auto-negotiation selects 100m as the highest performance mode. if the link partner is capable of half and full duplex modes, then auto-negotiation selects fu ll duplex as the highest performance operation. once a capability match has been determined, the link code words are repeated with the acknowledge bit set. any dif- ference in the main content of the link code words at this time will cause auto-negotiation to re-start. auto-negotiation will also re-start if not all of the required flp bursts are received. the capabilities advertised during auto-negotiation by the tran sceiver are initially determined by the logic levels latched on the mode[2:0] configuration straps af ter reset completes. these configuration straps can also be used to disable auto-negotiation on power-up. refer to section 3.7.2, "mode[2: 0]: mode configuration" for additional information. writing the bits 8 through 5 of the auto negotiation advertisement register allows software control of the capabilities advertised by the transceiver. writing the auto negotiation advertisement register does not automatically re-start auto- negotiation. the restart auto-negotiate bit of the basic control register must be set before the new abilities will be advertised. auto-negotiation can also be disabled via software by clearing the auto-negotiation enable bit of the basic control register . 3.2.1 parallel detection if the lan8741a/lan8741ai is connected to a device lacking t he ability to auto-negotiate (i.e., no flps are detected), it is able to determine the speed of the link based on ei ther 100m mlt-3 symbols or 10m normal link pulses. in this case the link is presumed to be half duplex per the ieee standard. this ability is known as ?parallel detection.? this feature ensures interoperability with legacy link partners. if a link is formed via parallel detection, then the link partner auto-negotiation able bit of the auto negotiation expansion register is cleared to indicate that the link partner is not capable of auto-negotiation. the controller has access to this information via the management interface. if a fault occurs during parallel detection, the parallel detection fault bit of link partner auto-negotiation able is set. auto negotiation link partner ability register is used to store the link partner ab ility information, which is coded in the received flps. if the link partner is not auto-negotiation capable, then the auto negotiation link partner ability register is updated after completion of parallel detection to reflect the speed capability of the link partner. 3.2.2 restarting auto-negotiation auto-negotiation can be restart ed at any time by setting the restart auto-negotiate bit of the basic control register . auto-negotiation will also restart if the link is broken at any time. a broken link is caused by signal loss. this may occur because of a cable break, or because of an interruption in the signal transmitted by the link partner. auto-negotiation resumes in an attempt to determine the new link configuration. if the management entity re-start s auto-negotiation by setting the restart auto-negotiate bit of the basic control reg- ister , the lan8741a/lan8741ai will respond by stopping all tr ansmission/receiving operations. once the break_link_- timer is completed in the auto-negotiation state-machine (appr oximately 1250 ms), auto-negotiation will re-start. in this case, the link partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negoti- ation. 3.2.3 disabling auto-negotiation auto-negotiation can be disabled by setting the auto-negotiation enable bit of the basic control register to zero. the device will then force its speed of operat ion to reflect the information in the basic control register ( speed select bit and duplex mode bit). these bits should be ignored when auto-negotiation is enabled. 3.2.4 half vs. full duplex half duplex operation relies on the csma/cd (carrier sense mu ltiple access / collision detect) protocol to handle net- work traffic and collisions. in this mode , the carrier sense signal, crs, responds to both transmit and receive activity. if data is received while the transceiver is transmitting, a collision results. in full duplex mode, the transceiver is able to transmit and receive data simultaneously. in this mode, crs responds only to receive activity. the csma/cd protocol does not apply and collision detection is disabled.
? 2013-2015 microchip technology inc. ds00001988a-page 23 lan8741a/lan8741ai 3.3 hp auto-mdix support hp auto-mdix facilitates the use of cat-3 (10base-t) or cat-5 (100base-tx) media utp interconnect cable without consideration of interface wiri ng scheme. if a user plugs in either a direct connect lan cable, or a cross-over patch cable, as shown in figure 3-4 , the device?s auto-mdix transceiver is capa ble of configuring th e txp/txn and rxp/rxn pins for correct transceiver operation. the internal logic of the device detects the tx and rx pi ns of the connecting device. si nce the rx and tx line pairs are interchangeable, special pcb design considerations are needed to accommodate the symmetrical magnetics and termination of an auto-mdix design. the auto-mdix function can be disabled via the amdixctrl bit in the special control/status indications register . note: when operating in 10base-t or 100base-tx manual modes, the auto-mdix crossover time can be extended via the extend manual 10/100 auto-mdix crossover time bit of the edpd nlp/crossover time/eee configur ation register . refer to section 4.2.12, "edpd nlp/cr ossover time/eee configura- tion register" for additional information. figure 3-4: direct cable connection vs. cross-over cable connection 1 2 3 4 5 6 7 8 txp txn rxp not used not used rxn not used not used 1 2 3 4 5 6 7 8 txp txn rxp not used not used rxn not used not used direct connect cable rj-45 8-pin straight-through for 10base-t/100base-tx signaling 1 2 3 4 5 6 7 8 txp txn rxp not used not used rxn not used not used 1 2 3 4 5 6 7 8 txp txn rxp not used not used rxn not used not used cross-over cable rj-45 8-pin cross-over for 10base-t/100base-tx signaling
lan8741a/lan8741ai ds00001988a-page 24 ? 2013-2015 microchip technology inc. 3.4 mac interface the mii/rmii block is responsible for communication with the mac controller. special sets of hand-shake signals are used to indicate that valid received/transmitted data is present on the 4 bit receive/transmit bus. the device must be configured in mii or rmii mode. this is done by specific pin strapping configurations. refer to sec- tion 3.4.3, "mii vs. rmii configuration" for information on pin strapping and how the pins are mapped differently. 3.4.1 mii the mii includes 16 interface signals: ? transmit data - txd[3:0] ? transmit strobe - txen ? transmit clock - txclk ? transmit error - txer/txd4 ? receive data - rxd[3:0] ? receive strobe - rxdv ? receive clock - rxclk ? receive error - rxer/rxd4/phyad0 ? collision indication - col ? carrier sense - crs in mii mode, on the transmit path, the transceiver drives the transmit clock, txclk, to the controller. the controller syn- chronizes the transmit data to the rising edge of txclk. the co ntroller drives txen high to indicate valid transmit data. the controller drives txer high when a transmit error is detected. on the receive path, the transceiver drives both the receiv e data, rxd[3:0], and the rxclk signal. the controller clocks in the receive data on the rising edge of rxclk when the transceiver drives rxdv high. the transceiver drives rxer high when a receive error is detected. 3.4.2 rmii the device supports the low pin count reduced media indepen dent interface (rmii) intended for use between ethernet transceivers and switch asics. u nder ieee 802.3, an mii comprised of 16 pins for data and control is defined. in devices incorporating many macs or transceiver interfaces such as s witches, the number of pins c an add significant cost as the port counts increase. rmii reduces this pin count while reta ining a management interface (m dio/mdc) that is identical to mii. the rmii interface has the following characteristics: ? it is capable of supporting 10 mbps and 100 mbps data rates ? a single clock reference is used for both transmit and receive ? it provides independent 2-bit (di-bit) wide transmit and receive data paths ? it uses lvcmos signal levels, compatible with common digital cmos asic processes the rmii includes the following interface signals (1 optional): ? transmit data - txd[1:0] ? transmit strobe - txen ? receive data - rxd[1:0] ? receive error - rxer (optional) ? carrier sense - crs_dv ? reference clock - (rmii references usually define this signal as ref_clk)
? 2013-2015 microchip technology inc. ds00001988a-page 25 lan8741a/lan8741ai 3.4.2.1 crs_dv - carrier sense/receive data valid the crs_dv is asserted by the device when the receive m edium is non-idle. crs_dv is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. in 10base-t mode when squelch is passed, or in 100base-tx mode when 2 non- contiguous zeroes in 10 bits are detected, the carrier is said to be detected. loss of carrier shall result in the deassertion of crs_dv synchronous to the cycle of ref_clk which presents the first di-bit of a nibble onto rxd[1:0] (i.e., crs_dv is deassert ed only on nibble boundaries). if the device has additional bits to be presented on rxd[1:0] following the in itial deassertion of crs_dv, then the device s hall assert crs_dv on cycles of ref_clk which present the second di -bit of each nibble and de-assert crs _dv on cycles of ref_clk which pres- ent the first di-bit of a nibble. the result is, starting on nibble boundaries, crs_dv toggles at 25 mhz in 100 mbps mode and 2.5 mhz in 10 mbps mode when crs ends before rxdv (i.e ., the fifo still has bits to transfer when the carrier event ends). therefore, the mac can accurately recover rxdv and crs. during a false carrier event, crs_dv shall remain asserted for the duration of carrier ac tivity. the data on rxd[1:0] is considered valid once crs_dv is asserted. however, since the assertion of crs_dv is asynchronous relative to ref_clk, the data on rxd[1:0] shall be ?00? until proper receive signal decoding takes place. 3.4.2.2 reference clock (ref_clk) the rmii ref_clk is a continuous clock that provides t he timing reference for crs_dv, rxd[1:0], txen, txd[1:0] and rxer. the device uses ref_clk as the network clock such that no buffering is required on the transmit data path. however, on the receive data path, the receiver recovers the clock from the incoming data stream, and the device uses elasticity buffering to accommodate for differences between the recovered clock and the local ref_clk.
lan8741a/lan8741ai ds00001988a-page 26 ? 2013-2015 microchip technology inc. 3.4.3 mii vs. rmii configuration the device must be configured to support the mii or rmii bus for connectivity to the mac. this configuration is done via the rmiisel configuration strap. mii or rmii mode selection is configured based on the strappi ng of the rmiisel configuration strap as described in section 3.7.3, "rmiisel: mi i/rmii mode configuration" . most of the mii and rmii pins are multiplexed. table 3-2, "mii/rmii signal mapping" describes the relationship of the related device pins to the mii and rmii mode signal names. note 1: the rxer signal is optional on the rmii bus. this signal is required by the transceiver, but it is optional for the mac. the mac can choose to ignore or not use this signal. 2: in rmii mode, this pin needs to be tied to vss. table 3-2: mii/rmii signal mapping pin name mii mode rmii mode txd0 txd0 txd0 txd1 txd1 txd1 txen txen txen rxer/ rxd4/phyad0 rxer rxer (see note 1 ) col/crs_dv/mode2 col crs_dv rxd0/mode0 rxd0 rxd0 rxd1/mode1 rxd1 rxd1 txd2 txd2 (see note 2 ) txd3 txd3 (see note 2 ) nint/txer/txd4 txer/ txd4 crs crs rxdv rxdv rxd2/rmiisel rxd2 rxd3/phyad2 rxd3 txclk txclk rxclk/phyad1 rxclk xtal1/clkin xtal1/clkin ref_clk
? 2013-2015 microchip technology inc. ds00001988a-page 27 lan8741a/lan8741ai 3.5 serial management interface (smi) the serial management interface is used to control the device and obtain its status. this interface supports registers 0 through 6 as required by clause 22 of the 802.3 standard, as well as ?vendor-specifi c? registers 16 to 31 allowed by the specification. device r egisters are detailed in chapter 4, "register descriptions" . at the system level, smi provides 2 si gnals: mdio and mdc. t he mdc signal is an aperio dic clock provided by the station management controller (smc). mdio is a bi-directio nal data smi input/output signal that receives serial data (commands) from the controller smc a nd sends serial data (status) to the smc. the minimum time between edges of the mdc is 160 ns. there is no maximu m time between edges. the minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400 ns. these modest timing requirements allow this interface to be easily driven by the i/o port of a microcontroller. the data on the mdio line is latched on the rising edge of the mdc. the frame structure and ti ming of the data is shown in figure 3-5 and figure 3-6 . the timing relationships of the mdio signals are further described in section 5.6.5, "smi timing" . figure 3-5: mdio timing and frame structure - read cycle figure 3-6: mdio timing and frame structure - write cycle mdc mdio read cycle ... 32 1's 0110a4a3a2a1a0r4r3r2r1r0 d1 ... d15 d14 d0 preamble start of frame op code phy address register address turn around data data from phy data to phy mdc mdio ... 32 1's 0 1 1 0 a4a3a2a1a0r4r3r2r1r0 write cycle d15 d14 d1 d0 ... data preamble start of frame op code phy address register address turn around data to phy
lan8741a/lan8741ai ds00001988a-page 28 ? 2013-2015 microchip technology inc. 3.6 interrupt management the device management interface supports an interrupt capability that is not a part of the ieee 802.3 specif ication. this interrupt capability generates an active low asynchronous in terrupt signal on the nint output whenever certain events are detected as setup by the interrupt mask register . the device?s interrupt system provides two modes, a primar y interrupt mode and an alternative interrupt mode. both systems will assert the nint pin low when the corresponding mask bit is set. these modes differ only in how they de- assert the nint interrupt output. these mode s are detailed in the following subsections. 3.6.1 primary interrupt system the primary interrupt system is the default interrupt mode ( altint bit of the mode control/status register is ?0?). the primary interrupt system is always selected after power-up or hard reset. in this mode, to set an interrupt, set the cor- responding mask bit in the interrupt mask register (see table 3-3 ). then when the event to assert nint is true, the nint output will be asserted. when the corresponding event to dea ssert nint is true, then the nint will be de-asserted. note 1: if the mask bit is enabled and nint has been de-asse rted while energyon is st ill high, nint will assert for 256 ms, approximately one second after energyon goes low when the cable is unplugged. to prevent an unexpected assertion of nint, the energyon interr upt mask should always be cleared as part of the energyon interrupt service routine. note: the primary interrupt mode is the default interrupt mode after a power-up or hard reset. the alternative interrupt mode requires setup after a power-up or hard reset. table 3-3: interrupt management table mask interrupt source flag interrupt source event to assert nint event to de-assert nint 30.7 29.7 energyon 17.1 ene rgyon rising 17.1 (see note 1 ) falling 17.1 or reading register 29 30.6 29.6 auto-negotiation complete 1.5 auto-negotiate complete rising 1.5 falling 1.5 or reading register 29 30.5 29.5 remote fault detected 1.4 remote fault rising 1.4 falling 1.4, or reading register 1 or reading register 29 30.4 29.4 link down 1.2 link status fa lling 1.2 reading register 1 or reading register 29 30.3 29.3 auto-negotiation lp acknowledge 5.14 acknowledge rising 5.14 falling 5.14 or reading register 29 30.2 29.2 parallel detection fault 6.4 parallel detec- tion fault rising 6.4 falling 6.4 or reading register 6, or reading register 29, or re-auto negotiate or link down 30.1 29.1 auto-negotiation page received 6.1 page received rising 6.1 falling 6.1 or reading register 6, or reading register 29, or re-auto negotiate, or link down. note: the energyon bit in the mode control/status register is defaulted to a ?1? at the start of the signal acqui- sition process, therefore the int7 bit in the interrupt mask register will also read as a ?1? at power-up. if no signal is present, then both energyon and int7 will clear within a few milliseconds.
? 2013-2015 microchip technology inc. ds00001988a-page 29 lan8741a/lan8741ai 3.6.2 alternate interrupt system the alternate interrupt system is enabled by setting the altint bit of the mode control/status register to ?1?. in this mode, to set an interrupt, set the corresponding bit of the in the mask register 30, (see table 3-4 ). to clear an interrupt, either clear the corresponding bit in the interrupt mask register to deassert the nint output, or clear the interrupt source, and write a ?1? to the corresponding interrupt source flag. writing a ?1? to the interrupt source flag will cause the state machine to check the interrupt source to determine if the interrupt source flag should clear or stay as a ?1?. if the condition to deassert is true, then the interrupt source flag is cleared and nint is also deasserted. if the condition to deassert is false, then the interrupt source flag remains set, and the nint remains asserted. for example, setting the int7 bit in the interrupt mask register will enable the energyon interrupt. after a cable is plugged in, the energyon bit in the mode control/status register goes active and nint will be asserted low. to de- assert the nint interrupt output, either clear the energyon bit in the mode control/status register by removing the cable and then writing a ?1? to the int7 bit in the interrupt mask register , or clear the int7 mask (bit 7 of the interrupt mask register ). table 3-4: alternative interrupt system management table mask interrupt source flag interrupt source event to assert nint condition to deassert bit to clear nint 30.7 29.7 energyon 17.1 energyon rising 17.1 17.1 low 29.7 30.6 29.6 auto-negotiation complete 1.5 auto-negotiate complete rising 1.5 1.5 low 29.6 30.5 29.5 remote fault detected 1.4 remote fault rising 1.4 1.4 low 29.5 30.4 29.4 link down 1.2 link status falling 1.2 1.2 high 29.4 30.3 29.3 auto-negotiation lp acknowledge 5.14 acknowledge rising 5.14 5.14 low 29.3 30.2 29.2 parallel detection fault 6.4 parallel detec- tion fault rising 6.4 6.4 low 29.2 30.1 29.1 auto-negotiation page received 6.1 page received rising 6.1 6.1 low 29.1 note: the energyon bit in the mode control/status register is defaulted to a ?1? at the start of the signal acqui- sition process, therefore the int7 bit in the interrupt mask register will also read as a ?1? at power-up. if no signal is present, then both energyon and int7 will clear within a few milliseconds.
lan8741a/lan8741ai ds00001988a-page 30 ? 2013-2015 microchip technology inc. 3.7 configuration straps configuration straps allow various features of the device to be automatically c onfigured to user defined values. config- uration straps are latched upon power-o n reset (por) and pin reset (nrst). configuration straps include internal resistors in order to prevent the signal fr om floating when unconnected. if a part icular configuration strap is connected to a load, an external pull-up or pull-down resistor should be used to augment the internal resistor to ensure that it reaches the required voltage level prior to latching. the in ternal resistor can also be overridden by the addition of an external resistor. 3.7.1 phyad[2:0] : phy address configuration the phyad[2:0] configuration straps are driven hi gh or low to give each phy a uniq ue address. this address is latched into an internal register at the end of a hardware reset ( default = 000b). in a multi-tran sceiver application (such as a repeater), the controller is able to manage each transcei ver via the unique address. ea ch transceiver checks each man- agement data frame for a matching address in the relevant bits. when a match is recognized, the transceiver responds to that particular frame. the phy address is also used to seed the scrambler. in a multi- transceiver application, this ensures that the scramblers are out of synchronization and disperses the electromagnetic radiation across the fre- quency spectrum. the device?s smi address may be configured using hardware configuration to any value between 0 and 7. the user can configure the phy address using software configuration if an address greater than 7 is required. the phy address can be written (after smi communication at some address is established) using the phyad bits of the special modes reg- ister . the phyad[2:0] configuration straps are multiple xed with other signals as shown in table 3-5 . note: the system designer must g uarantee that configurati on strap pins meet the ti ming requirements specified in section 5.6.2, "power-on nrst & configuration strap timing" . if configuration str ap pins are not at the correct voltage level prior to being latched, the device may capture incorrect strap values. note: when externally pulling configuration straps high, th e strap should be tied to vddio, except for regoff and nintsel which should be tied to vdd2a. table 3-5: pin names for address bits address bit pin name phyad[0] rxer/rxd4/phyad0 phyad[1] rxclk/phyad1 phyad[2] rxd3/phyad2
? 2013-2015 microchip technology inc. ds00001988a-page 31 lan8741a/lan8741ai 3.7.2 mode[2:0] : mode configuration the mode[2:0] configuration straps control the configuration of the 10/100 digital block. when the nrst pin is deas- serted, the register bit values ar e loaded according to the mode[2:0] configuration straps. the 10/100 digital block is then configured by the register bit val ues. when a soft reset occurs via the soft reset bit of the basic control register , the configuration of the 10 /100 digital block is controlled by the register bit values and the mode[2:0] configuration straps have no affect. the device?s mode may be configured using the hardware configuration straps as summarized in table 3-6 . the user may configure the transceiver mode by writing the smi registers. the mode[2:0] hardware configuration pins ar e multiplexed with other signals as shown in table 3-7 . table 3-6: mode[2:0] bus mode[2:0] mode definitions default register bit values register 0 register 4 [13,12,10,8] [8,7,6,5] 000 10base-t half duplex. auto-n egotiation disabled. 0000 n/a 001 10base-t full duplex. auto-n egotiation disabled. 0001 n/a 010 100base-tx half duplex. auto-negotiation disabled. crs is active during transmit & receive. 1000 n/a 011 100base-tx full duplex. auto-negotiation disabled. crs is active during receive. 1001 n/a 100 100base-tx half duplex is advertised. auto-negoti- ation enabled. crs is active during transmit & receive. 1100 0100 101 repeater mode. auto-negotiation enabled. 100base-tx half duplex is advertised. crs is active during receive. 1100 0100 110 power-down mode. in this mode the transceiver will wake-up in power-down mode. the transceiver can- not be used when the mode[2:0] bits are set to this mode. to exit this mode, the mode bits in register 18.7:5 (see section 4.2.14, "special modes register" ) must be configured to some other value and a soft reset must be issued. n/a n/a 111 all capable. auto-negotiation enabled. x10x 1111 table 3-7: pin names for mode bits mode bit pin name mode[0] rxd0/mode0 mode[1] rxd1/mode1 mode[2] col/crs_dv/mode2
lan8741a/lan8741ai ds00001988a-page 32 ? 2013-2015 microchip technology inc. 3.7.3 rmiisel : mii/rmii mode configuration mii or rmii mode selection is latched on the rising edge of the internal reset (nrst) based on the strapping of the rmiisel configuration strap. the default mode is mii (via the in ternal pull-down resistor). to select rmii mode, pull the rmiisel configuration strap high with an external resistor to vddio. when the nrst pin is deasserted, the miimode bit of the special modes register is loaded according to the rmiisel configuration strap. the m ode is reflected in the miimode bit of the special modes register . refer to section 3.4, "mac interface" for additional information on mii and rmii modes. 3.7.4 regoff : internal +1.2 v regulator configuration the incorporation of flexpwr technology pr ovides the ability to disable the internal +1.2 v regulator. when the regulator is disabled, an external +1.2 v must be supplied to the vddcr pin. disabling the internal +1.2 v regulator makes it possible to reduce total system power, since an external sw itching regulator with greater efficiency (versus the internal linear regulator) can be used to provide +1.2 v to the transceiver circuitry. 3.7.4.1 disabling the internal +1.2 v regulator to disable the +1.2 v internal regulator, a pull-up str apping resistor should be connected from the regoff configura- tion strap to vdd2a. at power-on, after both vddio and v dd2a are within specif ication, the transceiver will sample regoff to determine whether the internal regulator should turn on. if the pin is sampled at a voltage greater than v ih , then the internal regulator is disabled and the system mu st supply +1.2 v to the vddcr pin. the vddio voltage must be at least 80% of the operating voltage level (1.44 v when o perating at 1.8 v, 2.0 v when operating at 2.5 v, 2.64 v when operating at 3.3 v) before voltage is applied to vddcr. as described in section 3.7.4.2 , when regoff is left floating or connected to vss, t he internal regulator is enabled and the system is not required to s upply +1.2 v to the vddcr pin. 3.7.4.2 enabling the internal +1.2 v regulator the +1.2 v for vddcr is supplied by the on-chip regulator unless the transceiver is configured for the regulator off mode using the regoff configuration strap as described in section 3.7.4.1 . by default, the intern al +1.2 v regulator is enabled when regoff is floating (due to the internal pull-down resistor). during power-on, if regoff is sampled below v il , then the internal +1.2 v regulator will turn on and operate with power from the vdd2a pin. 3.7.5 n intsel : nint/txer/txd4 configuration the nint, txer, and txd4 functions share a common pin. ther e are two functional modes for this pin, the txer/txd4 mode and nint (interrupt) mode. the nintsel configuration strap is latched at por and on the rising edge of the nrst. by default, nintsel is configured for nint mode via the internal pull-up resistor. note: because the regoff configuration strap shares functionality with the led1 pin, proper consideration must also be given to the led polarity. refer to section 3.8.1, "leds" for additional information on the rela- tion between regoff and the led1 polarity. note: in order to utilize eee, th e nint/txer/txd4 pin must be configured as txer/txd4. note: because the nintsel configuration strap shares functionality with the led2 pin, proper consideration must also be given to the led polarity. refer to section 3.8.1.2, "nintsel and led2 polarity selection" for additional information on the relation between nintsel and the led2 polarity.
? 2013-2015 microchip technology inc. ds00001988a-page 33 lan8741a/lan8741ai 3.8 miscellaneous functions 3.8.1 leds two led signals are provided as a convenient means to indi cate the transceiver's mode of operation. all led signals are either active high or active low as described in section 3.8.1.1, "regoff and led1 polarity selection" and section 3.8.1.2, "nintsel and le d2 polarity selection" . the led1 output is driven active whenever the device detect s a valid link, and blinks when crs is active (high) indicat- ing activity. the led2 output is driven active when the operating speed is 100 mbps. this led will go inactive when the operating speed is 10 mbps or during line isolation. 3.8.1.1 regoff and led1 polarity selection the regoff configuration strap is shared with the led1 pin. the led1 output will automatically change polarity based on the presence of an external pull-up resistor. if the led1 pin is pulled high to vdd2a by an external pull-up resistor to select a logical high for regoff , then the led1 output will be active low. if the led1 pin is pulled low by the internal pull-down resistor to select a logical low for regoff , the led1 output will then be an active high output. figure 3-7 details the led1 polarity for each regoff configuration. note: when pulling the led1 and led2 pins high, they must be tied to vdd2a, not vddio. figure 3-7: led1/regoff polarity configuration note: refer to section 3.7.4, "regoff: internal +1.2 v regulator configuration" for additional information on the regoff configuration strap. led1/regoff ~270 ? regoff = 0 (regulator on) led output = active high ~270 ? vdd2a regoff = 1 (regulator off) led output = active low led1/regoff 10k
lan8741a/lan8741ai ds00001988a-page 34 ? 2013-2015 microchip technology inc. 3.8.1.2 nintsel and led2 polarity selection the nintsel configuration strap is shared wit h the led2 pin. the led2 output wil l automatically change polarity based on the presence of an external pull-down resistor. if the led2 pin is pulled high to vdd2a to select a logical high for nintsel , then the led2 output will be active low. if the led2 pin is pulled low by an external pull-down resistor to select a logical low for nintsel , the led2 output will then be an active high output. figure 3-8 details the led2 polarity for each nintsel configuration. 3.8.2 variable voltage i/o the device?s digital i/o pins are variable voltage, allowing them to take advantage of low power savings from shrinking technologies. these pins can oper ate from a low i/o voltage of +1.8 v up to +3.3 v. the applied i/o voltage must main- tain its value with a tolerance of 10%. varying the voltage up or down after the transceiver has completed power-on reset can cause errors in the transceiver operation. refer to chapter 5, "operational characteristics" for additional infor- mation. 3.8.3 power-down modes there are two device power-down modes: general power-d own mode and energy detect power-down mode. these modes are described in the following subsections. 3.8.3.1 general power-down this power-down mode is controlled via the power down bit of the basic control register . in this mode, the entire trans- ceiver (except the management interface) is powere d-down and remains in this mode as long as the power down bit is ?1?. when the power down bit is cleared, the transceiver pow ers up and is automatically reset. 3.8.3.2 energy detect power-down (edpd) this power-down mode is activated by setting the edpwrdown bit of the mode control/status register . in this mode, when no energy is present on the line the transceiver is powered down (except for the management interface, the squelch circuit, and the energyon logic). the energyon lo gic is used to detect the presence of valid energy from 100base-tx, 10base-t, or auto-negotiation signals. in this mode, when the energyon bit of the mode control/status register is low, the transceiver is powered-down and nothing is transmitted. when energy is received via link pulses or packets, the energyon bit goes high and the transceiver powers-up. the device automat ically resets into the state prior to power-down and asserts the nint interrupt if the energyon interrupt is enabled in the interrupt mask register . the first and possibly the second packet to acti- vate energyon may be lost. when the edpwrdown bit of the mode control/status register is low, energy detect power-down is disabled. figure 3-8: led2/n intsel polarity configuration note: refer to section 3.7.5, "nintsel: nint/txer/txd4 configuration" for additional information on the nint- sel configuration strap. note: input signals must not be driven high before power is applied to the device. ~270 ? nintsel = 0 led output = active high 10k ~270 ? vdd2a nintsel = 1 led output = active low led2/nintsel led2/nintsel
? 2013-2015 microchip technology inc. ds00001988a-page 35 lan8741a/lan8741ai when in edpd mode, the device?s nlp characteristics may be modified. the device can be configured to transmit nlps in edpd via the edpd tx nlp enable bit of the edpd nlp/crossover time/ eee configurat ion register . when enabled, the tx nlp time interval is configurable via the edpd tx nlp interval timer select field of the edpd nlp/crossover time/eee configurati on register . when in edpd mode, the device can also be configured to wake on the reception of one or two nlps. setting the edpd rx single nlp wake enable bit of the edpd nlp/crossover time/eee configuration register will enable the device to wake on reception of a single nlp. if the edpd rx single nlp wake enable bit is cleared, the maximum interval for detecting reception of two nlps to wake from edpd is con- figurable via the edpd rx nlp max interval detect select field of the edpd nlp/crossover time/eee configuration register . 3.8.4 energy efficient ethernet the device supports ieee 802.3az energy efficient ethern et (eee). the eee functionality is enabled/disabled via the phy energy efficient ethernet enable (phyeeeen) bit of the edpd nlp/crossover time/ eee configuration register . energy efficient ethernet is disabled by default. in order for eee to be utilized, the followi ng conditions must be met: ? the device must configured in mii mode (rmiisel configuration strap low) ? the nint/txer/txd4 pin must be configured as txer/txd4 (nintsel configuration strap low) ? eee functionality must be enabled via the phy energy efficient et hernet enable (phyeeeen) bit of the edpd nlp/crossover time/eee configuration register ?the 100base-tx eee bit of the mmd eee advertisement register must be set ? the selected mac and link-partner must support and be configured for eee operation ? the device and link-partner must link in 100base-tx full-duplex mode the value of the phy energy efficient et hernet enable (phyeeeen) bit affects the default values of the following reg- ister bits: ? 100base-tx eee bit of the mmd eee capability register ? 100base-tx eee bit of the mmd eee advertisement register 3.8.5 isolate mode the device data paths may be electrically is olated from the mii/rmii interface by setting the isolate bit of the basic con- trol register to ?1?. in isolation mode, the tr ansceiver does not respond to the txd, txen and txer inputs, but does respond to management transactions. isolation provides a means for multiple transceivers to be connected to the same mii/rmii interface without contention. by default, the transceiver is not isolated (on power-up ( isolate =0). 3.8.6 resets the device provides two forms of reset: hardware and soft ware. the device registers are reset by both hardware and software resets. select register bits, indicated as ?nasr? in the register definitions, are not cleared by a software reset. the registers are not reset by t he power-down modes described in section 3.8.3 . 3.8.6.1 hardware reset a hardware reset is asserted by driving the nrst input pin low. when driven, nrst should be held low for the minimum time detailed in section 5.6.2, "power-on nrst & configuration strap timing" to ensure a proper transceiver reset. during a hardware reset, an external clock must be supplied to the xtal1/clkin signal. note: eee cannot be used in rmii mode. note: for the first 16 s after coming out of reset, the mii/rm ii interface will run at 2.5 mhz. after this time, it will switch to 25 mhz if auto-negotiation is enabled. note: a hardware reset (nrst assertion) is required following power-up. refer to section 5.6.2, "power-on nrst & configuration strap timing" for additional information.
lan8741a/lan8741ai ds00001988a-page 36 ? 2013-2015 microchip technology inc. 3.8.6.2 software reset a software reset is ac tivated by setting the soft reset bit of the basic control register to ?1?. all registers bits, except those indicated as ?nasr? in the register defin itions, are cleared by a software reset. the soft reset bit is self-clearing. per the ieee 802.3u standard, clause 22 (22.2.4.1.1) the reset process will be completed within 0.5 s from the setting of this bit. 3.8.7 carrier sense the carrier sense (crs) is output on the crs pin in m ii mode, and the crs_dv pin in rmii mode. crs is a signal defined by the mii specificat ion in the ieee 802.3u standard. the device asserts crs based only on receive activity whenever the transceiver is either in repeater mode or full-duplex mode. ot herwise the transceiver asserts crs based on either transmit or receive activity. the carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. it activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. carrier sense terminates if a span of 10 con- secutive ones is detected before a /j/k / start-of stream delimiter pair. if an ssd pair is detected, carrier sense is asserted until either /t/r/ end?of-stream delimiter pair or a pair of idle symbols is detected. carrier is negated after the /t/ symbol or the first idle. if /t/ is not followed by /r/, then carrier is maintained. carrier is treated similarly for i dle followed by some non-idle symbol. 3.8.8 collision detect a collision is the occurrence of simultaneous transmit and rece ive operations. the col output is asserted to indicate that a collision has been detected. col remains active for the duration of the collision. col is changed asynchronously to both rxclk and txclk. the col output becom es inactive during full duplex mode. the col may be tested by setting the collision test bit of the basic control register to ?1?. this enables the collision test. col will be asserted within 512 bit times of txen rising and will be de-asserted within 4 bit times of txen falling. 3.8.9 link integrity test the device performs the lin k integrity test as outlined in the ieee 802.3u (c lause 24-15) link moni tor state diagram. the link status is multiplexed with the 10 mbps link status to form the link status bit in the basic status register and to drive the link led (led1). the dsp indicates a valid mlt-3 waveform present on the r xp and rxn signals as defined by the ansi x3.263 tp- pmd standard, to the link monitor state-machine, us ing the internal data_valid signal. when data_valid is asserted, the control logic moves into a link-ready state and waits for an enable from the auto-negotiation block. when received, the link-up state is entered, and the transmit and receive logic blocks become active. should auto-negoti- ation be disabled, the link integrity logic moves immediat ely to the link-up state when the data_valid is asserted. to allow the line to stabilize, the link integrity logic will wait a minimum of 330 ms from the time data_valid is asserted until the link-ready state is entered. should the data_valid input be negat ed at any time, this logic will immediately negate the link signal and enter the link-down state. when the 10/100 digital blo ck is in 10base-t mode, the link status is derived from the 10base-t receiver logic.
? 2013-2015 microchip technology inc. ds00001988a-page 37 lan8741a/lan8741ai 3.8.10 ? loopback operation the device may be configured for near-end loopback and far loopback. these loopback modes are detailed in the fol- lowing subsections. 3.8.10.1 near-end loopback near-end loopback mode sends the digital transmit data back out the receive data signals for testing purposes, as indi- cated by the blue arrows in figure 3-9 . the near-end loopback mode is enabled by setting the loopback bit of the basic control register to ?1?. a large percentage of the digital circuitry is operational in near-end loopback mode because data is routed through the pcs and pma layers into the pmd sublayer before it is looped back. the col signal will be inac- tive in this mode, unless collision test is enabled in the basic control register . the transmitters are powered down regardless of the state of txen. refer to section 5.6.3.1, "100 mbps internal loopback mii timing" for additional loop- back timing information. 3.8.10.2 far loopback far loopback is a special test mode for mdi (anal og) loopback as indicated by the blue arrows in figure 3-10 . the far loopback mode is enabled by setting the farloopback bit of the mode control/status register to ?1?. in this mode, data that is received from the link partner on the mdi is looped back out to the link partner. the digital interface signals on the local mac interface are isolated. figure 3-9: near-end loopback block diagram note: this special test mode is only available when operating in rmii mode. figure 3-10: far loop back block diagram microchip ethernet transceiver 10/100 ethernet mac cat-5 xfmr digital rxd txd analog rx tx x x far-end system microchip ethernet transceiver 10/100 ethernet mac cat-5 xfmr digital rxd txd analog rx tx link partner x x
lan8741a/lan8741ai ds00001988a-page 38 ? 2013-2015 microchip technology inc. 3.8.10.3 connector loopback the device maintains reliable transmission over very short cables and can be tested in a connector loopback as shown in figure 3-11 . an rj45 loopback cable can be used to route the tr ansmit signals from the output of the transformer back to the receiver inputs. the loopback works at both 10 and 100 mbps. figure 3-11: connector loopback block diagram microchip ethernet transceiver 10/100 ethernet mac xfmr digital rxd txd analog rx tx 1 2 3 4 5 6 7 8 rj45 loopback cable. created by connecting pin 1 to pin 3 and connecting pin 2 to pin 6.
? 2013-2015 microchip technology inc. ds00001988a-page 39 lan8741a/lan8741ai 3.9 application diagrams this section provides typical appl ication diagrams for the following: ? simplified system level application diagram ? power supply diagram (1.2 v supplied by internal regulator) ? power supply diagram (1.2 v supplied by external source) ? twisted-pair interface diagram (single power supply) ? twisted-pair interface diagram (dual power supplies) 3.9.1 simplified system l evel application diagram figure 3-12: simplified system level application diagram lan8741a/lan8741ai 10/100 phy 32-vqfn mii txp txn mag rj45 rxp rxn 25 mhz xtal1/clkin xtal2 txd[3:0] 4 rxd[3:0] rxclk rxdv 4 mii led[2:1] 2 interface mdio mdc nint nrst txclk txer txen
lan8741a/lan8741ai ds00001988a-page 40 ? 2013-2015 microchip technology inc. 3.9.2 power supply diagram (1.2 v supplied by internal regulator) figure 3-13: power supply diagram (1 .2 v supplied by internal regulator) lan8741a/lan8741ai 32-vqfn rbias vss 12.1k vdd2a c bypass c bypass vdd1a vddio c bypass c f vdddio supply 1.8 - 3.3 v power supply 3.3 v vddcr led1/ regoff ~270 ohm core logic internal regulator ch.2: 3.3 v circuitry in out ch.1: 3.3 v circuitry 470 pf 1 uf
? 2013-2015 microchip technology inc. ds00001988a-page 41 lan8741a/lan8741ai 3.9.3 power supply diagram (1.2 v supplied by external source) figure 3-14: power supply diagram (1 .2 v supplied by external source) lan8741a/lan8741ai 32-vqfn rbias vss 12.1k vdd2a c bypass c bypass vdd1a vddio c bypass c f vdddio supply 1.8 - 3.3 v power supply 3.3 v vddcr 470 pf led1/ regoff core logic internal regulator (disabled) ch.2: 3.3 v circuitry in out ch.1: 3.3 v circuitry vddcr supply 1.2 v ~270 ohm 10k 1 uf
lan8741a/lan8741ai ds00001988a-page 42 ? 2013-2015 microchip technology inc. 3.9.4 twisted-pair interface diagram (single power supply) figure 3-15: twisted-pair interface diagram (single power supply) magnetics lan8741a/lan8741ai 32-vqfn vdd2a c bypass txp txn power supply 3.3 v 1 2 3 4 5 6 7 8 1000 pf 3 kv rj45 75 ohm 75 ohm rxp rxn c bypass vdd1a c bypass 49.9 ohm resistors ferrite bead
? 2013-2015 microchip technology inc. ds00001988a-page 43 lan8741a/lan8741ai 3.9.5 twisted-pair interface diagram (dual power supplies) figure 3-16: twisted-pair interf ace diagram (dual power supplies) magnetics lan8741a/lan8741ai 32-vqfn vdd2a c bypass txp txn power supply 3.3 v 1 2 3 4 5 6 7 8 1000 pf 3 kv rj45 75 ohm 75 ohm rxp rxn c bypass vdd1a c bypass 49.9 ohm resistors power supply 2.5 v - 3.3 v
lan8741a/lan8741ai ds00001988a-page 44 ? 2013-2015 microchip technology inc. 4.0 register descriptions this chapter describes the various control and status registers (csrs) and mdio manageable device (mmd) regis- ters . the csrs follow the ieee 802.3 (c lause 22.2.4) management register set. the mmd registers adhere to the ieee 802.3-2008 45.2 mdio interface registers specification. all functionality and bit definitions comply with these stan- dards. the ieee 802.3 specified register index (in decimal) is includ ed with each csr definitio n, allowing fo r addressing of these registers via the serial manage ment interface (smi) protocol. mmd regi sters are accessed indirectly via the mmd access control register and mmd access address/data register csrs. 4.1 register nomenclature table 4-1 describes the register bit attribute notation used throughout this document. many of these register bit notations can be comb ined. some examples of this are shown below: ? r/w: can be written. will return current setting on a read. ? r/wac: will return current setting on a read. writing anything clears the bit. table 4-1: register bit types register bit type notation register bit description r read: a register or bit with this attribute can be read. w write: a register or bit with th is attribute can be written. ro read only: writes have no effect. wo write only: if a register or bit is write-only, reads will return unspecified data. wc write one to clear: writing a one clears the value. writing a zero has no effect wac write anything to clear: writing anything clears the value. rc read to clear: contents is cleared after th e read. writes have no effect. ll latch low: clear on read of register. lh latch high: clear on read of register. sc self-clearing: contents are self-cleared after the being set. writes of zero have no effect. contents can be read. ss self-setting: contents are self-setting after being cleared. writes of one have no effect. contents can be read. ro/lh read only, latch high: bits with this attribute will stay high until the bit is read. after it is read, the bit will either remain high if the high condition remains, or will go low if the high condition has been removed. if the bit has not been read, the bit will remain high regardless of a change to the high condition . this mode is used in some ethernet phy registers. nasr not affected by software reset: the state of nasr bits do not change on assertion of a software reset. reserved reserved field: reserved fields must be written with zeros to ensure future compati- bility. the value of reserved bits is not guaranteed on a read.
? 2013-2015 microchip technology inc. ds00001988a-page 45 lan8741a/lan8741ai 4.2 control and status registers table 4-2 provides a list of supported register s. register details, including bit defin itions, are provided in the proceeding subsections. table 4-2: smi register map register index (decimal) register name group 0 basic control register basic 1 basic status register basic 2 phy identifier 1 register extended 3 phy identifier 2 register extended 4 auto negotiation advertisement register extended 5 auto negotiation link partner ability register extended 6 auto negotiation expansion register extended 7 auto negotiation next page tx register extended 8 auto negotiation next page rx register extended 13 mmd access control register extended 14 mmd access address/data register extended 16 edpd nlp/crossover time/ eee configuration register vendor-specific 17 mode control/status register vendor-specific 18 special modes register vendor-specific 26 symbol error counter register vendor-specific 27 special control/status indications register vendor-specific 29 interrupt source flag register vendor-specific 30 interrupt mask register vendor-specific 31 phy special control/status register vendor-specific
lan8741a/lan8741ai ds00001988a-page 46 ? 2013-2015 microchip technology inc. 4.2.1 basic control register note 1: the default value of this bit is determined by the mode[2:0] configuration straps. refer to section 3.7.2, "mode[2:0]: mode configuration" for additional information. index (in decimal): 0 size: 16 bits bits description type default 15 soft reset 1 = software reset. bit is self-clearing. when setting this bit do not set other bits in this register. note: the configuration (as described in section 3.7.2, "mode[2:0]: mode configuration" ) is set from the register bit values, and not from the mode pins. r/w sc 0b 14 loopback 0 = normal operation 1 = loopback mode r/w 0b 13 speed select 0 = 10 mbps 1 = 100 mbps note: ignored if auto-negotiation is enabled (0.12 = 1). r/w (see note 1 ) 12 auto-negotiation enable 0 = disable auto-negotiate process 1 = enable auto-negotiate process (overrides 0.13 and 0.8) r/w (see note 1 ) 11 power down 0 = normal operation 1 = general power down mode r/w 0b 10 isolate 0 = normal operation 1 = electrical isolation of phy from the mii/rmii r/w 0b 9 restart auto-negotiate 0 = normal operation 1 = restart auto-negotiate process note: bit is self-clearing. r/w sc 0b 8 duplex mode 0 = half duplex 1 = full duplex note: ignored if auto-negotiation is enabled (0.12 = 1). r/w (see note 1 ) 7 collision test 0 = disable col test 1 = enable col test r/w 0b 6:0 reserved ro -
? 2013-2015 microchip technology inc. ds00001988a-page 47 lan8741a/lan8741ai 4.2.2 basic status register index (in decimal): 1 size: 16 bits bits description type default 15 100base-t4 0 = no t4 ability 1 = t4 able ro 0b 14 100base-tx full duplex 0 = no tx full duplex ability 1 = tx with full duplex ro 1b 13 100base-tx half duplex 0 = no tx half duplex ability 1 = tx with half duplex ro 1b 12 10base-t full duplex 0 = no 10 mbps with full duplex ability 1 = 10 mbps with full duplex ro 1b 11 10base-t half duplex 0 = no 10 mbps with half duplex ability 1 = 10 mbps with half duplex ro 1b 10 100base-t2 full duplex 0 = phy is not able to perform full duplex 100base-t2 1 = phy is able to perfor m full duplex 100base-t2 ro 0b 9 100base-t2 half duplex 0 = phy is not able to perform half duplex 100base-t2 1 = phy is able to perfor m half duplex 100base-t2 ro 0b 8 extended status 0 = no extended status information in register 15 1 = extended status information in register 15 ro 0b 7:6 reserved ro - 5 auto-negotiate complete 0 = auto-negotiate process not completed 1 = auto-negotiate process completed ro 0b 4 remote fault 1 = remote fault condition detected 0 = no remote fault ro/lh 0b 3 auto-negotiate ability 0 = unable to perform auto-negotiation function 1 = able to perform auto-negotiation function ro 1b 2 link status 0 = link is down. 1 = link is up. ro/ll 0b 1 jabber detect 0 = no jabber condition detected. 1 = jabber condition detected. ro/lh 0b 0 extended capabilities 0 = does not support extended capabilities registers 1 = supports extended capabilities registers ro 1b
lan8741a/lan8741ai ds00001988a-page 48 ? 2013-2015 microchip technology inc. 4.2.3 phy identi fier 1 register index (in decimal): 2 size: 16 bits bits description type default 15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (oui), respectively. r/w 0007h
? 2013-2015 microchip technology inc. ds00001988a-page 49 lan8741a/lan8741ai 4.2.4 phy identi fier 2 register index (in decimal): 3 size: 16 bits bits description type default 15:10 phy id number assigned to the 19th through 24th bits of the oui. r/w c120h 9:4 model number six-bit manufacturer?s model number r/w 3:0 revision number four-bit manufacturer?s revision number r/w note: the default value of the revision number field may vary dependent on the silicon revision number.
lan8741a/lan8741ai ds00001988a-page 50 ? 2013-2015 microchip technology inc. 4.2.5 auto negotiation advertisement register note 1: the default value of this bit is determined by the mode[2:0] configuration straps. refer to section 3.7.2, "mode[2:0]: mode configuration" for additional information. index (in decimal): 4 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable r/w 0b 14 reserved ro - 13 remote fault 0 = no remote fault 1 = remote fault detected r/w 0b 12 reserved ro - 11:10 pause operation 00 = no pause 01 = symmetric pause 10 = asymmetric pause toward link partner 11 = advertise support for both symmetric pause and asymmetric pause toward local device note: when both symmetric pause and asymmetric pause are set, the device will only be configured to, at most, one of the two settings upon auto-negotiation completion. r/w 00b 9 reserved ro - 8 100base-tx full duplex 0 = no tx full duplex ability 1 = tx with full duplex r/w (see note 1 ) 7 100base-tx 0 = no tx ability 1 = tx able r/w 1b 6 10base-t full duplex 0 = no 10 mbps with full duplex ability 1 = 10 mbps with full duplex r/w (see note 1 ) 5 10base-t 0 = no 10 mbps ability 1 = 10 mbps able r/w (see note 1 ) 4:0 selector field 00001 = ieee 802.3 r/w 00001b
? 2013-2015 microchip technology inc. ds00001988a-page 51 lan8741a/lan8741ai 4.2.6 auto negotiation link partner ability register index (in decimal): 5 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable ro 0b 14 acknowledge 0 = link code word not yet received 1 = link code word received from partner ro 0b 13 remote fault 0 = no remote fault 1 = remote fault detected ro 0b 12 reserved ro - 11:10 pause operation 00 = no pause supported by partner station 01 = symmetric pause supported by partner station 10 = asymmetric pause supported by partner station 11 = both symmetric pause and asy mmetric pause supported by partner station ro 00b 9 100base-t4 0 = no t4 ability 1 = t4 able note: this device does not support t4 ability. ro 0b 8 100base-tx full duplex 0 = no tx full duplex ability 1 = tx with full duplex ro 0b 7 100base-tx 0 = no tx ability 1 = tx able ro 0b 6 10base-t full duplex 0 = no 10 mbps with full duplex ability 1 = 10 mbps with full duplex ro 0b 5 10base-t 0 = no 10 mbps ability 1 = 10 mbps able ro 0b 4:0 selector field 00001 = ieee 802.3 ro 00001b
lan8741a/lan8741ai ds00001988a-page 52 ? 2013-2015 microchip technology inc. 4.2.7 auto negotiation expansion register index (in decimal): 6 size: 16 bits bits description type default 15:7 reserved ro - 6 receive next page location able 0 = received next page storage loca tion is not specified by bit 6.5 1 = received next page storage location is specified by bit 6.5 ro 1b 5 received next page storage location 0 = link partner next pages are stored in the auto negotiation link partner ability register (phy register 5) 1 = link partner next pages are stored in the auto negotiation next page rx register (phy register 8) ro 1b 4 parallel detection fault 0 = no fault detected by parallel detection logic 1 = fault detected by parallel detection logic ro/lh 0b 3 link partner next page able 0 = link partner does not have next page ability. 1 = link partner has next page ability. ro 0b 2 next page able 0 = local device does not have next page ability. 1 = local device has next page ability. ro 1b 1 page received 0 = new page not yet received 1 = new page received ro/lh 0b 0 link partner auto -negotiation able 0 = link partner does not have auto-negotiation ability. 1 = link partner has auto-negotiation ability. ro 0b
? 2013-2015 microchip technology inc. ds00001988a-page 53 lan8741a/lan8741ai 4.2.8 auto negotiation next page tx register index (in decimal): 7 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable r/w 0b 14 reserved ro - 13 message page 0 = unformatted page 1 = message page r/w 1b 12 acknowledge 2 0 = device cannot co mply with message. 1 = device will comply with message. r/w 0b 11 toggle 0 = previous value was high. 1 = previous value was low. ro 0b 10:0 message code message/unformatted code field r/w 000 0000 0001b
lan8741a/lan8741ai ds00001988a-page 54 ? 2013-2015 microchip technology inc. 4.2.9 auto negotiation next page rx register index (in decimal): 8 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable ro 0b 14 acknowledge 0 = link code word not yet received from partner 1 = link code word received from partner ro 0b 13 message page 0 = unformatted page 1 = message page ro 0b 12 acknowledge 2 0 = device cannot co mply with message. 1 = device will comply with message. ro 0b 11 toggle 0 = previous value was high. 1 = previous value was low. ro 0b 10:0 message code message/unformatted code field ro 000 0000 0000b
? 2013-2015 microchip technology inc. ds00001988a-page 55 lan8741a/lan8741ai 4.2.10 mmd access control register this register in conjunction with the mmd access address/data register provides indirect access to the mdio man- ageable device (mmd) registers. refer to section 4.3, "mdio manageable device (mmd) registers" for additional details. index (in decimal): 13 size: 16 bits bits description type default 15:14 mmd function this field is used to select the desired mmd function: 00 = address 01 = data, no post increment 10 = reserved 11 = reserved r/w 00b 13:5 reserved ro - 4:0 mmd device address (devad) this field is used to select the desired mmd device address. (3 = pcs, 7 = auto-negotiation) r/w 0h
lan8741a/lan8741ai ds00001988a-page 56 ? 2013-2015 microchip technology inc. 4.2.11 mmd access address/data register this register in conjunction with the mmd access control register provides indirect access to the mdio manageable device (mmd) registers. refer to section 4.3, "mdi o manageable device (mmd) registers" for additional details. index (in decimal): 14 size: 16 bits bits description type default 15:0 mmd register address/data if the mmd function field of the mmd access control register is ?00?, this field is used to indicate the mmd regist er address to read/write of the device specified in the mmd device address (devad) field. otherwise, this register is used to read/write data from/to the previously specified mmd address. r/w 0000h
? 2013-2015 microchip technology inc. ds00001988a-page 57 lan8741a/lan8741ai 4.2.12 edpd nl p/crossover time/eee co nfiguration register index (in decimal): 16 size: 16 bits bits description type default 15 edpd tx nlp enable when in energy detect power-down (edpd) mode ( edpwrdown =1), this bit enables the transmission of single tx nlps at the interval defined by the edpd tx nlp interval timer select field. 0 = tx nlp disabled 1 = tx nlp enabled when in edpd mode r/w nasr 0b 14:13 edpd tx nlp interval timer select when in energy detect power-down (edpd) mode ( edpwrdown = 1) and edpd tx nlp enable is 1, this field defines t he interval used to send single tx nlps. 00 = 1 second (default) 01 = 768 ms 10 = 512 ms 11 = 256 ms r/w nasr 00b 12 edpd rx single nlp wake enable when in energy detect power-down (edpd) mode ( edpwrdown =1), this bit enables waking the phy on reception of a single rx nlp. 0 = rx nlp wake disabled 1 = tx nlp wake enabled when in edpd mode r/w nasr 0b 11:10 edpd rx nlp max interval detect select when in energy detect power-down (edpd) mode ( edpwrdown = 1) and edpd rx single nlp wake enable is 0, this field defines the maximum inter- val for detecting two rx nlps to wake from edpd mode 00 = 64 ms (default) 01 = 256 ms 10 = 512 ms 11 = 1 second r/w nasr 00b 9:3 reserved ro - 2 phy energy efficient et hernet enable (phyeeeen) when set, e nables energy efficient ethernet (eee) ope ration in the phy. when cleared, eee oper ation is disabled. refer to section 3.8.4, "energy efficient ethernet" for additional information. r/w nasr 0b 1 edpd extend crossover when in energy detect power-down (edpd) mode ( edpwrdown =1), setting this bit to 1 extends the crossover time by 2976 ms. 0 = crossover time extension disabled 1 = crossover time extension enabled (2976 ms) r/w nasr 0b 0 extend manual 10/100 auto-mdix crossover time when auto-midx is enabled and the phy is in manual 10base-t or 100base-tx mode, setting this bit to 1 extends the crossover time by 1984 ms to allow linking to an auto-negotiation link partner phy. 0 = crossover time extension disabled 1 = crossover time extension enabled (1984 ms) r/w nasr 1b
lan8741a/lan8741ai ds00001988a-page 58 ? 2013-2015 microchip technology inc. 4.2.13 mode contro l/status register index (in decimal): 17 size: 16 bits bits description type default 15:14 reserved ro - 13 edpwrdown enable the energy detect power-down (edpd) mode: 0 = energy detect power-down is disabled. 1 = energy detect power-down is enabled. note: when in edpd mode, the device ?s nlp characteristics can be modified via the edpd nlp/crossover time/eee configuration register . r/w 0b 12:10 reserved ro - 9 farloopback enables far loopback mode (i.e., all the received packets are sent back simul- taneously (in 100base-tx only)). this bit is only active in rmii mode. this mode works even if the isolate bit (0.10) is set. 0 = far loopback mode is disabled. 1 = far loopback mode is enabled. refer to section 3.8.10.2, "far loopback" for additional information. r/w 0b 8:7 reserved ro - 6 altint alternate interrupt mode: 0 = primary interrupt system enabled (default) 1 = alternate interrupt system enabled refer to section 3.6, "interrupt management" for additional information. r/w 0b 5:2 reserved ro - 1 energyon indicates whether energy is detected. this bit transitions to ?0? if no valid energy is detected within 256 ms. it is re set to ?1? by a hardware reset and is unaffected by a software reset. refer to section 3.8.3.2, "energy detect power-down (edpd)" for additional information. ro 1b 0 reserved r/w 0b
? 2013-2015 microchip technology inc. ds00001988a-page 59 lan8741a/lan8741ai 4.2.14 special modes register note 1: the default value of this field is determined by the rmiisel configuration strap. refer to section 3.7.3, "rmiisel: mii/rmii mode configuration" for additional information. 2: the default value of this field is determined by the mode[2:0] configuration straps. refer to section 3.7.2, "mode[2:0]: mode configuration" for additional information. 3: the default value of this field is determined by the phyad[0] configuration strap. refer to section 3.7.1, "phyad[2:0]: phy address configuration" for additional information. index (in decimal): 18 size: 16 bits bits description type default 15 reserved ro - 14 miimode reflects the mode of the digital interface: 0 = mii mode 1 = rmii mode ro (see note 1 ) 13:8 reserved ro - 7:5 mode transceiver mode of operation. refer to section 3.7.2, "m ode[2:0]: mode configuration" for additional details. r/w nasr (see note 2 ) 4:0 phyad phy address. the phy address is used for the smi address and for initializa- tion of the cipher (scrambler) key. refer to section 3.7.1, "phyad[2:0]: phy address configuration" for additional details. r/w nasr (see note 3 )
lan8741a/lan8741ai ds00001988a-page 60 ? 2013-2015 microchip technology inc. 4.2.15 symbol error counter register index (in decimal): 26 size: 16 bits bits description type default 15:0 symbol error counter (sym_err_cnt) this 100base-tx receiver-based error counter increments when an invalid code symbol is received, including idle symbols. the counter is incremented only once per packet, even when the received packet contains more than one symbol error. this field counts up to 65, 536 and rolls over to 0 if incremented beyond it?s maximum value. note: this register is cleared on reset, but is not cleared by reading the register. it does not increment in 10base-t mode. ro 0000h
? 2013-2015 microchip technology inc. ds00001988a-page 61 lan8741a/lan8741ai 4.2.16 special control/stat us indications register index (in decimal): 27 size: 16 bits bits description type default 15 amdixctrl hp auto-mdix control: 0 = enable auto-mdix 1 = disable auto-mdix (use 27.13 to control channel) r/w nasr 0b 14 reserved ro - 13 ch_select manual cha nnel select: 0 = mdi (tx transmits, rx receives) 1 = mdix (tx receives, rx transmits) r/w nasr 0b 12 reserved ro - 11 sqeoff disable the sqe test (heartbeat): 0 = sqe test is enabled 1 = sqe test is disabled r/w nasr 0b 10:5 reserved ro - 4 xpol polarity state of the 10base-t: 0 = normal polarity 1 = reversed polarity ro 0b 3:0 reserved ro -
lan8741a/lan8741ai ds00001988a-page 62 ? 2013-2015 microchip technology inc. 4.2.17 interrupt source flag register index (in decimal): 29 size: 16 bits bits description type default 15:8 reserved ro - 7 int7 0 = not source of interrupt 1 = energyon generated ro/lh 0b 6 int6 0 = not source of interrupt 1 = auto-negotiation complete ro/lh 0b 5 int5 0 = not source of interrupt 1 = remote fault detected ro/lh 0b 4 int4 0 = not source of interrupt 1 = link down (link status negated) ro/lh 0b 3 int3 0 = not source of interrupt 1 = auto-negotiation lp acknowledge ro/lh 0b 2 int2 0 = not source of interrupt 1 = parallel detection fault ro/lh 0b 1 int1 0 = not source of interrupt 1 = auto-negotiation page received ro/lh 0b 0 reserved ro 0b
? 2013-2015 microchip technology inc. ds00001988a-page 63 lan8741a/lan8741ai 4.2.18 interrupt mask register index (in decimal): 30 size: 16 bits bits description type default 15:8 reserved ro - 7:1 mask bits these bits mask the corresponding interrupts in the interrupt source flag register . 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0000000b 0 reserved ro -
lan8741a/lan8741ai ds00001988a-page 64 ? 2013-2015 microchip technology inc. 4.2.19 phy special control/status register index (in decimal): 31 size: 16 bits bits description type default 15:13 reserved ro - 12 autodone auto-negotiation done indication: 0 = auto-negotiation is not done or disabled (or not active). 1 = auto-negotiation is done. ro 0b 11:7 reserved ro - 6 enable 4b5b 0 = bypass encoder/decoder 1 = enable 4b5b encoding/decoding. mac interface must be configured in mii mode. r/w 1b 5 reserved ro - 4:2 speed indication hcdspeed value: 001 = 10base-t half-duplex 101 = 10base-t full-duplex 010 = 100base-tx half-duplex 110 = 100base-tx full-duplex ro xxxb 1:0 reserved ro -
? 2013-2015 microchip technology inc. ds00001988a-page 65 lan8741a/lan8741ai 4.3 mdio manageable device (mmd) registers the device mmd registers adhere to the ieee 802.3-2008 45.2 mdio interface registers specification. the mmd reg- isters are not memory mapped. these regi sters are accessed indirectly via the mmd access control register and mmd access address/data register . the supported mmd device addresses are 3 (pcs), 7 (auto-negotiation), and 30 (ven- dor specific). table 4-3, "mmd registers" details the supported regist ers within each mmd device. to read or write an mmd register, the following procedure must be observed: 1. write the mmd access control register with 00b (address) for the mmd function field and the desired mmd device (3 for pcs, 7 for auto-negotiation) for the mmd device address (devad) field. 2. write the mmd access address/data register with the 16-bit address of the desir ed mmd register to read/write within the previously selected mmd device (pcs or auto-negotiation). 3. write the mmd access control register with 01b (data) for the mmd function field and choose the previously selected mmd device (3 for pcs, 7 for auto-negotiation) for the mmd device address (devad) field. 4. if reading, read the mmd access address/data register , which contains the select ed mmd register contents. if writing, write the mmd access address/data register with the register contents intended for the previously selected mmd register. table 4-3: mmd registers mmd device address (in decimal) index (in decimal) register name 3 (pcs) 0 pcs control 1 register 1 pcs status 1 register 5 pcs mmd devices present 1 register 6 pcs mmd devices present 2 register 20 eee capability register 22 eee wake error register 7 (auto-negotiation) 5 auto-negotiation mmd devices present 1 register 6 auto-negotiation mmd devices present 2 register 60 eee advertisement register 61 eee link partner advertisement register 30 (vendor specific) 2 vendor specific mmd 1 device id 1 register 3 vendor specific mmd 1 device id 2 register 5 vendor specific 1 mmd devices present 1 register 6 vendor specific 1 mmd devices present 2 register 8 vendor specific mmd 1 status register 14 vendor specific mmd 1 package id 1 register 15 vendor specific mmd 1 package id 2 register
lan8741a/lan8741ai ds00001988a-page 66 ? 2013-2015 microchip technology inc. 4.3.1 pcs control 1 register index (in decimal): 3.0 size: 16 bits bits description type default 15:11 reserved ro - 10 clock stop enable 0 = the phy cannot stop the clock during low power idle (lpi). 1 = the phy may stop the clock during lpi. note: the device does not support this mode. r/w 0b 9:0 reserved ro -
? 2013-2015 microchip technology inc. ds00001988a-page 67 lan8741a/lan8741ai 4.3.2 pcs status 1 register index (in decimal): 3.1 size: 16 bits bits description type default 15:12 reserved ro - 11 tx lpi received 0 = tx pcs has not received lpi. 1 = tx pcs has received lpi. ro/lh 0b 10 rx lpi received 0 = rx pcs has not received lpi. 1 = rx pcs has received lpi. ro/lh 0b 9 tx lpi indication 0 = tx pcs is not currently receiving lpi. 1 = tx pcs is currently receiving lpi. ro 0b 8 rx lpi indication 0 = rx pcs is not currently receiving lpi. 1 = rx pcs is currently receiving lpi. ro 0b 7 reserved ro - 6 clock stop capable 0 = the mac cannot stop the clock during low power idle (lpi). 1 = the mac may stop the clock during lpi. note: the device does not support this mode. ro 0b 5:0 reserved ro -
lan8741a/lan8741ai ds00001988a-page 68 ? 2013-2015 microchip technology inc. 4.3.3 pcs mmd devic es present 1 register index (in decimal): 3.5 size: 16 bits bits description type default 15:8 reserved ro - 7 auto-negotiation present 0 = auto-negotiation not present in package 1 = auto-negotiation present in package ro 1b 6 tc present 0 = tc not present in package 1 = tc present in package ro 0b 5 dte xs present 0 = dte xs not present in package 1 = dte xs present in package ro 0b 4 phy xs present 0 = phy xs not present in package 1 = phy xs present in package ro 0b 3 pcs present 0 = pcs not present in package 1 = pcs present in package ro 1b 2 wis present 0 = wis not present in package 1 = wis present in package ro 0b 1 pmd/pma present 0 = pmd/pma not present in package 1 = pmd/pma present in package ro 0b 0 clause 22 registers present 0 = clause 22 registers not present in package 1 = clause 22 registers present in package ro 0b
? 2013-2015 microchip technology inc. ds00001988a-page 69 lan8741a/lan8741ai 4.3.4 pcs mmd devic es present 2 register index (in decimal): 3.6 size: 16 bits bits description type default 15 vendor specific device 2 present 0 = vendor specific device 2 not present in package 1 = vendor specific device 2 present in package ro 0b 14 vendor specific device 1 present 0 = vendor specific device 1 not present in package 1 = vendor specific device 1 present in package ro 1b 13 clause 22 extension present 0 = clause 22 extension not present in package 1 = clause 22 extension present in package ro 0b 12:0 reserved ro -
lan8741a/lan8741ai ds00001988a-page 70 ? 2013-2015 microchip technology inc. 4.3.5 eee capability register note 1: the default value of this field is determined by the value of the phy energy efficient ethernet enable (phy- eeeen) of the edpd nlp/crossover time/eee configuration register . if phy energy efficient ethernet enable (phyeeeen) is 0b, this field is 0b and 100base- tx eee capability is not supported. if phy energy efficient ethernet enable (phyeeeen) is 1b, then this field is 1b and 100base-tx eee capability is sup- ported. index (in decimal): 3.20 size: 16 bits bits description type default 15:7 reserved ro - 6 10gbase-kr eee 0 = eee is not supported for 10gbase-kr. 1 = eee is supported for 10gbase-kr. note: the device does not support this mode. ro 0b 5 10gbase-kx4 eee 0 = eee is not supported for 10gbase-kx4. 1 = eee is supported for 10gbase-kx4. note: the device does not support this mode. ro 0b 4 10gbase-kx eee 0 = eee is not supported for 10gbase-kx. 1 = eee is supported for 10gbase-kx. note: the device does not support this mode. ro 0b 3 10gbase-t eee 0 = eee is not supported for 10gbase-t. 1 = eee is supported for 10gbase-t. note: the device does not support this mode. ro 0b 2 1000base-t eee 0 = eee is not supported for 1000base-t. 1 = eee is supported for 1000base-t. note: the device does not support this mode. ro 0b 1 100base-tx eee 0 = eee is not supported for 100base-tx. 1 = eee is supported for 100base-tx. ro (see note 1 ) 0 reserved ro -
? 2013-2015 microchip technology inc. ds00001988a-page 71 lan8741a/lan8741ai 4.3.6 eee wake error register index (in decimal): 3.22 size: 16 bits bits description type default 15:0 eee wake error counter this counter is cleared to zeros on read and is held to all ones on overflow. ro/rc 0000h
lan8741a/lan8741ai ds00001988a-page 72 ? 2013-2015 microchip technology inc. 4.3.7 auto-negotiation mmd devices present 1 register index (in decimal): 7.5 size: 16 bits bits description type default 15:8 reserved ro - 7 auto-negotiation present 0 = auto-negotiation not present in package 1 = auto-negotiation present in package ro 1b 6 tc present 0 = tc not present in package 1 = tc present in package ro 0b 5 dte xs present 0 = dte xs not present in package 1 = dte xs present in package ro 0b 4 phy xs present 0 = phy xs not present in package 1 = phy xs present in package ro 0b 3 pcs present 0 = pcs not present in package 1 = pcs present in package ro 1b 2 wis present 0 = wis not present in package 1 = wis present in package ro 0b 1 pmd/pma present 0 = pmd/pma not present in package 1 = pmd/pma present in package ro 0b 0 clause 22 registers present 0 = clause 22 registers not present in package 1 = clause 22 registers present in package ro 0b
? 2013-2015 microchip technology inc. ds00001988a-page 73 lan8741a/lan8741ai 4.3.8 auto-negotiation mmd devices present 2 register index (in decimal): 7.6 size: 16 bits bits description type default 15 vendor specific device 2 present 0 = vendor specific device 2 not present in package 1 = vendor specific device 2 present in package ro 0b 14 vendor specific device 1 present 0 = vendor specific device 1 not present in package 1 = vendor specific device 1 present in package ro 1b 13 clause 22 extension present 0 = clause 22 extension not present in package 1 = clause 22 extension present in package ro 0b 12:0 reserved ro -
lan8741a/lan8741ai ds00001988a-page 74 ? 2013-2015 microchip technology inc. 4.3.9 eee advertisement register note 1: this bit is read/write (r/w). however, the user must not set this bit if eee is disabled. 2: the default value of this field is determined by the value of the phy energy efficient ethernet enable (phy- eeeen) of the edpd nlp/crossover time/eee conf iguration register on page 57 . if phy energy efficient ethernet enable (phyeeeen) is 0b, this field is 0b and 100base-tx eee capability is not advertised. if phy energy efficient ethe rnet enable (phyeeeen) is 1b, then this field is 1b and 100base-tx eee capa- bility is advertised. index (in decimal): 7.60 size: 16 bits bits description type default 15:2 reserved ro - 1 100base-tx eee 0 = do not advertise eee capability for 100base-tx. 1 = advertise eee capability for 100base-tx. (see note 1 )(see note 2 ) 0 reserved ro -
? 2013-2015 microchip technology inc. ds00001988a-page 75 lan8741a/lan8741ai 4.3.10 eee link partner advertisement register index (in decimal): 7.61 size: 16 bits bits description type default 15:7 reserved ro - 6 10gbase-kr eee 0 = link partner does not advert ise eee capability for 10gbase-kr. 1 = link partner advertises eee capability for 10gbase-kr. note: this device does not support this mode. ro 0b 5 10gbase-kx4 eee 0 = link partner does not advert ise eee capability for 10gbase-kx4. 1 = link partner advertises eee capability for 10gbase-kx4. note: this device does not support this mode. ro 0b 4 10gbase-kx eee 0 = link partner does not advert ise eee capability for 10gbase-kx. 1 = link partner advertises eee capability for 10gbase-kx. note: this device does not support this mode. ro 0b 3 10gbase-t eee 0 = link partner does not advert ise eee capability for 10gbase-t. 1 = link partner advertises eee capability for 10gbase-t. note: this device does not support this mode. ro 0b 2 1000base-t eee 0 = link partner does not advert ise eee capability for 1000base-t. 1 = link partner advertises eee capability for 1000base-t. note: this device does not support this mode. ro 0b 1 100base-tx eee 0 = link partner does not advert ise eee capability for 100base-tx. 1 = link partner advertises eee capability for 100base-tx. ro 0b 0 reserved ro -
lan8741a/lan8741ai ds00001988a-page 76 ? 2013-2015 microchip technology inc. 4.3.11 vendor specific mmd 1 device id 1 register index (in decimal): 30.2 size: 16 bits bits description type default 15:0 reserved ro 0000h
? 2013-2015 microchip technology inc. ds00001988a-page 77 lan8741a/lan8741ai 4.3.12 vendor specific mmd 1 device id 2 register index (in decimal): 30.3 size: 16 bits bits description type default 15:0 reserved ro 0000h
lan8741a/lan8741ai ds00001988a-page 78 ? 2013-2015 microchip technology inc. 4.3.13 vendor specific 1 mmd devices present 1 register index (in decimal): 30.5 size: 16 bits bits description type default 15:8 reserved ro - 7 auto-negotiation present 0 = auto-negotiation not present in package 1 = auto-negotiation present in package ro 1b 6 tc present 0 = tc not present in package 1 = tc present in package ro 0b 5 dte xs present 0 = dte xs not present in package 1 = dte xs present in package ro 0b 4 phy xs present 0 = phy xs not present in package 1 = phy xs present in package ro 0b 3 pcs present 0 = pcs not present in package 1 = pcs present in package ro 1b 2 wis present 0 = wis not present in package 1 = wis present in package ro 0b 1 pmd/pma present 0 = pmd/pma not present in package 1 = pmd/pma present in package ro 0b 0 clause 22 registers present 0 = clause 22 registers not present in package 1 = clause 22 registers present in package ro 0b
? 2013-2015 microchip technology inc. ds00001988a-page 79 lan8741a/lan8741ai 4.3.14 vendor specific 1 mmd devices present 2 register index (in decimal): 30.6 size: 16 bits bits description type default 15 vendor specific device 2 present 0 = vendor specific device 2 not present in package 1 = vendor specific device 2 present in package ro 0b 14 vendor specific device 1 present 0 = vendor specific device 1 not present in package 1 = vendor specific device 1 present in package ro 1b 13 clause 22 extension present 0 = clause 22 extension not present in package 1 = clause 22 extension present in package ro 0b 12:0 reserved ro -
lan8741a/lan8741ai ds00001988a-page 80 ? 2013-2015 microchip technology inc. 4.3.15 vendor specific mmd 1 status register index (in decimal): 30.8 size: 16 bits bits description type default 15:14 device present 00 = no device responding at this address 01 = no device responding at this address 10 = device responding at this address 11 = no device responding at this address 10b 13:0 reserved ro -
? 2013-2015 microchip technology inc. ds00001988a-page 81 lan8741a/lan8741ai 4.3.16 vendor specific mmd 1 package id 1 register index (in decimal): 30.14 size: 16 bits bits description type default 15:0 reserved ro 0000h
lan8741a/lan8741ai ds00001988a-page 82 ? 2013-2015 microchip technology inc. 4.3.17 vendor specific mmd 1 package id 2 register index (in decimal): 30.15 size: 16 bits bits description type default 15:0 reserved ro 0000h
? 2013-2015 microchip technology inc. ds00001988a-page 83 lan8741a/lan8741ai 5.0 operational characteristics 5.1 absolute maximum ratings* supply voltage (vddio, vdd1a, vdd2a) (see note 1 ).......................................................................... -0.5 v to +3.6 v digital core supply voltage (vddcr) (see note 1 ) ................................................................................ -0.5 v to +1.5 v ethernet magnetics supply voltage .............................................................................................. ........... -0.5 v to +3.6 v positive voltage on input signal pins, with respect to ground (see note 2 ) ............................................... vddio + 2.0 v negative voltage on input signal pins, with respect to ground (see note 3 ) ............................................................-0.5 v positive voltage on xtal1/clkin, with respect to grou nd ........................................................................ ...............3.6 v storage temperature ............................................................................................................ ..................-55 o c to +150 o c lead temperature range .......................................... ................................................. refer to jedec spec. j-std-020 hbm esd performance ............................................................................................................ ............ .jedec class 3a note 1: when powering this device from laboratory or system powe r supplies, it is important that the absolute max- imum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists , it is suggested that a clamp circuit be used. 2: this rating does not apply to the follo wing pins: xtal1/clkin, xtal2, rbias. 3: this rating does not apply to the following pins: rbias. *stresses exceeding those listed in th is section could cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating conditions for extended periods may affect device reliability. functional operation of the device at any condition exceeding those indicated in section 5.2, "operating conditions**" or any other applicable section of this specification is not implied. note, device signals are not 5.0 v tolerant unless specified oth- erwise. 5.2 operating conditions** supply voltage (vddio) ......................................................................................................... .............. +1.62 v to +3.6 v analog port supply voltage (vdd1a, vdd2a) ............. ......................................................................... . +3.0 v to +3.6 v digital core supply voltage (vddcr) ............ .............. .............. .............. .............. .............. .......... .... +1.14 v to +1.26 v ethernet magnetics supply voltage .............................................................................................. ........ +2.25 v to +3.6 v ambient operating temperature in still air (t a )........................................................................................... (see note 1 ) note 1: 0c to +70c for commercial version, -40c to +85c for industrial version. **proper operation of the device is guar anteed only within the ranges specified in this section. after the device has com- pleted power-up, vddio and the magnetics power supply must maintain their voltage level with 10%. varying the volt- age greater than 10% after the device has completed power-up can cause errors in device operation. 5.3 package thermal specifications note: do not drive input signals without power supplied to the device. table 5-1: package thermal parameters parameter symbol value unit comment thermal resistance ja 47.8 o c/w measured in still air from the die to ambient air junction-to-top-of-package jt 0.7 o c/w measured in still air note: thermal parameters are measured or estimated fo r devices in a multi-layer 2s2p pcb per jesd51.
lan8741a/lan8741ai ds00001988a-page 84 ? 2013-2015 microchip technology inc. 5.4 power consumption this section details the device power measurements tak en over various operating condi tions. unless otherwise noted, all measurements were taken with power supplies at nomi nal values (vddio, vdd1a, vdd2a = 3.3 v, vddcr = 1.2 v). see section 3.8.3, "power-down modes" for a description of the power down modes. 5.4.1 regulator disabled 5.4.2 regulator enabled table 5-2: current consumption and power dissipation (reg. disabled) power pin group 3.3 v device current (ma) 1.2 v device current (ma) 3.3 v device current w/ magnetics (ma) total device power (mw) nreset typical 9.7 11 9.7 45 100base-tx /w traffic (no eee) typical 32 21 74 130 10base-t /w traffic typical 11 13 114 51 100base-tx idle /w eee typical 32 15 32 122 energy detect power down typical 4.0 1.7 4.0 15 general power down typical 0.3 1.4 0.4 2.8 table 5-3: current consumption and power dissipation (reg. enabled) power pin group device current (ma) device current w/ magnetics (ma) total device power (mw) nreset typical 21 21 70 100base-tx /w traffic (no eee) typical 55 97 180 10base-t /w traffic typical 25 129 82 100base-tx idle /w eee typical 48 48 158 energy detect power down typical 7.1 7.1 24 general power down typical 4.0 4.0 13
? 2013-2015 microchip technology inc. ds00001988a-page 85 lan8741a/lan8741ai 5.5 dc specifications table 5-4 details the non-variable i/o buffer characteristics. these buffer types do not support variable voltage opera- tion. table 5-5 details the variable voltage i/o buffer characteristics. typical values are provided for 1.8 v, 2.5 v, and 3.3 v vddio cases. note 1: this specification applies to all inputs and tri-stated bi-directional pins. internal pull-down and pull-up resis- tors add 50 a per-pin (typical). 2: xtal1/clkin can optionally be driven from a 25 mhz single-ended clock oscillator. table 5-4: non-variable i/o buffer characteristics parameter symbol min. typ. max. unit note is type input buffer low input level high input level negative-going threshold positive-going threshold schmitt trigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vddio) input capacitance v ili v ihi v ilt v iht v hys i ih c in -0.3 1.01 1.39 336 -10 1.19 1.59 399 3.6 1.39 1.79 459 10 2 v v v v mv a pf schmitt trigger schmitt trigger (see note 1 ) o12 type buffers low output level high output level v ol v oh vdd2a - 0.4 0.4 v v i ol = 12 ma i oh = -12 ma iclk type buffer (xtal1 input) low input level high input level v ili v ihi -0.3 vddcr-0.35 0.35 3.6 v v (see note 2 )
lan8741a/lan8741ai ds00001988a-page 86 ? 2013-2015 microchip technology inc. note 1: this specification applies to all inputs and tri-stated bi-directional pins. internal pull-down and pull-up resis- tors add 50 a per-pin (typical). table 5-5: variable i/o buffer characteristics parameter symbol min. 1.8 v typ. 2.5 v typ. 3.3 v typ. max. unit note vis type input buffer low input level high input level neg-going threshold pos-going threshold schmitt trigger hystere- sis (v iht - v ilt ) input leakage (v in = vss or vddio) input capacitance v ili v ihi v ilt v iht v hys i ih c in -0.3 0.64 0.81 102 -10 0.83 0.99 158 1.15 1.29 136 1.41 1.65 138 3.6 1.76 1.90 288 10 2 v v v v mv a pf schmitt trigger schmitt trigger (see note 1 ) vo8 type buffers low output level high output level v ol v oh vddio - 0.4 0.4 v v i ol = 8 ma i oh = -8 ma vod8 type buffer low output level v ol 0.4 v i ol = 8 ma
? 2013-2015 microchip technology inc. ds00001988a-page 87 lan8741a/lan8741ai note 1: measured at line side of transformer, line replaced by 100 ? (1%) resistor. 2: offset from 16 ns pulse width at 50% of pulse peak. 3: measured differentially. note 1: min/max voltages guaranteed as measured with 100 ? resistive load. 5.6 ac specifications this section details the various ac timing specifications of the device. 5.6.1 equivalent test load output timing specifications assume a 25 pf equivalent test load, unless otherwis e noted, as illustrated in figure 5-1 below. table 5-6: 100base-tx transceiver characteristics parameter symbol min. typ. max. unit note peak differential output voltage high v pph 950 - 1050 mvpk (see note 1 ) peak differential output voltage low v ppl -950 - -1050 mvpk (see note 1 ) signal amplitude symmetry v ss 98 - 102 % (see note 1 ) signal rise and fall time t rf 3.0 - 5.0 ns (see note 1 ) rise and fall symmetry t rfs - - 0.5 ns (see note 1 ) duty cycle distortion d cd 35 50 65 % (see note 2 ) overshoot and undershoot v os --5% jitter 1.4 ns (see note 3 ) table 5-7: 10base-t tran sceiver characteristics parameter symbol min. typ. max. unit note transmitter peak differential output voltage v out 2.2 2.5 2.8 v (see note 1 ) receiver differential squelch threshold v ds 300 420 585 mv figure 5-1: output eq uivalent test load 25 pf output
lan8741a/lan8741ai ds00001988a-page 88 ? 2013-2015 microchip technology inc. 5.6.2 power-on nrst & co nfiguration strap timing this diagram illustrates the nrst reset and configuration st rap timing requirements in relation to power-on. a hardware reset (nrst assertion) is required following power-up. for proper operation, nrst must be asserted for no less than t rstia. the nrst pin can be asserted at any time, but must not be deasserted before t purstd after all external power sup- plies have reached operational levels. in order for valid co nfiguration strap values to be read at power-up, the t css and t csh timing constraints must be followed. refer to section 3.8.6, "resets" for additional information. note 1: 20 clock cycles for 25 mhz, or 40 clock cycles for 50 mhz figure 5-2: power-on nrst & configuration strap timing table 5-8: power-on nrst & co nfiguration strap timing values symbol description min. typ. max. unit t purstd external power supplies at operational level to nrst deassertion 25 ms t purstv external power supplies at operational level to nrst valid 0ns t rstia nrst input assertion time 100 s t css configuration strap pins setup to nrst deassertion 200 ns t csh configuration strap pins hold after nrst deassertion 1 ns t otaa output tri-state after nrst assertion 50 ns t odad output drive after nrst deassertion 2 800 (see note 1 ) ns note: nrst deassertion must be monotonic. note: device configuration straps are latched as a result of nrst assertion. refer to section 3.7, "configuration straps" for details. configuration straps must only be pul led high or low and must not be driven as inputs. t css nrst configuration strap pins input t rstia t csh configuration strap pins output drive t odad all external power supplies t purstd v opp t purstv t otaa
? 2013-2015 microchip technology inc. ds00001988a-page 89 lan8741a/lan8741ai 5.6.3 mii interface timing this section specifies the mii interface tr ansmit and receive timing. please refer to section 3.4.1, "mii" for additional details. note 1: 40 ns for 100base-tx operation, 400 ns for 10base-t operation. 2: timing was designed for system load between 10 pf and 25 pf. figure 5-3: mii receive timing table 5-9: mii receive timing values symbol description min. typ. max. unit note t clkp rxclk period (see note 1 )ns t clkh rxclk high time t clkp * 0.4 t clkp * 0.6 ns t clkl rxclk low time t clkp * 0.4 t clkp * 0.6 ns t val rxd[3:0], rxdv, rxer output valid from rising edge of rxclk 28.0 ns (see note 2 ) t invld rxd[3:0], rxdv, rxer output invalid from rising edge of rxclk 10.0 ns (see note 2 ) rxclk (output) t clkh t clkl t clkp t val t invld t val t val t invld rxdv, rxer (outputs) rxd[3:0] (outputs)
lan8741a/lan8741ai ds00001988a-page 90 ? 2013-2015 microchip technology inc. note 1: 40 ns for 100base-tx operation, 400 ns for 10base-t operation. 2: timing was designed for system load between 10 pf and 25 pf. figure 5-4: mii transmit timing table 5-10: mii transmit timing values symbol description min. typ. max. unit note t clkp txclk period (see note 1 )ns t clkh txclk high time t clkp * 0.4 t clkp * 0.6 ns t clkl txclk low time t clkp * 0.4 t clkp * 0.6 ns t su txd[3:0], txen, txer setup time to rising edge of txclk 12.0 ns (see note 2 ) t hold txd[3:0], txen, txer hold time after rising edge of txclk 0ns(see note 2 ) t 1 txclk rising edge after txen assertion to rxdv assertion (100 mbps internal loopback mode) 160 162 ns (see note 2 ) t su t clkh t clkl t clkp t hold t su t hold t hold t su t hold txclk (output) txd[3:0] (inputs) txen, txer (inputs)
? 2013-2015 microchip technology inc. ds00001988a-page 91 lan8741a/lan8741ai 5.6.3.1 100 mbps internal loopback mii timing figure 5-5: 100 mbps inte rnal loopback mii timing table 5-11: 100 mbps internal loopback mii timing values symbol description min. typ. max. unit t 1 txclk rising edge after txen assertion to rxdv assertion (100 mbps internal loopback mii mode) 160 161 162 ns note: the t 1 measurement applies in mii mode when the loopback bit of the basic control register is set to ?1? and a link has been established in 100 mb full-duplex mode. the t 1 measurement is taken from the first rising edge of txclk following assertion of txen to the rising edge of rxdv. txclk (output) rxd[3:0] (outputs) txen (input) t 1 rxdv (output)
lan8741a/lan8741ai ds00001988a-page 92 ? 2013-2015 microchip technology inc. 5.6.4 rmii interface timing this section specifies t he rmii interface transmit and receive timing. note 1: timing was designed for system load between 10 pf and 25 pf. note: the crs_dv pin performs both carrier sense and data va lid functions. crs_dv is asserted asynchro- nously on detection of carrier due to the criteria re levant to the operating mode. if the phy has additional bits to be presented on rxd[1:0] following the initial deassertion of crs_dv, then the device will assert crs_dv on cycles of ref_clk which present the seco nd di-bit of each ni bble and deassert crs_dv on cycles of ref_clk which present the first di-bit of a nibble. for addit ional information, refer to the rmii specification. figure 5-6: rmii timing table 5-12: rmii timing values symbol description min. typ. max. unit note t clkp clkin period 20 ns t clkh clkin high time t clkp * 0.35 t clkp * 0.65 ns t clkl clkin low time t clkp * 0.35 t clkp * 0.65 ns t oval rxd[1:0], rxer, crs_dv output valid from rising edge of clkin 15.0 ns (see note 1 ) t oinvld rxd[1:0], rxer, crs_dv output invalid from rising edge of clkin 3.0 ns (see note 1 ) t su txd[1:0], txen setup time to ris- ing edge of clkin 4.0 ns (see note 1 ) t ihold txd[1:0], txen input hold time after rising edge of clkin 1.5 ns (see note 1 ) t clkh t clkl t clkp t oval t oinvld t oval t oval t oinvld t su t ihold t su t ihold t ihold t su t ihold clkin (ref_clk) (input) rxd[1:0], rxer (outputs) crs_dv (output) txd[1:0] (inputs) txen (input)
? 2013-2015 microchip technology inc. ds00001988a-page 93 lan8741a/lan8741ai 5.6.4.1 rmii clkin requirements 5.6.5 smi timing this section specifies the smi timing of the device. please refer to section 3.5, "serial management interface (smi)" for additional details. table 5-13: rmii clkin (ref_clk) timing values parameter min. typ. max. unit note clkin frequency 50 mhz clkin frequency drift 50 ppm clkin duty cycle 40 60 % clkin jitter 150 ps p-p ? not rms figure 5-7: smi timing table 5-14: smi timing values symbol description min. max. unit t clkp mdc period 400 ns t clkh mdc high time 160 (80%) ns t clkl mdc low time 160 (80%) ns t val mdio (read from phy) output valid from rising edge of mdc 300 ns t oinvld mdio (read from phy) output invalid from rising edge of mdc 0 ns t su mdio (write to phy) setup ti me to rising edge of mdc 10 ns t ihold mdio (write to phy) in put hold time after rising edge of mdc 10 ns mdc mdio t clkh t clkl t clkp t oinvld mdio t su t ihold (data-out) (data-in) t oinvld t val (input)
lan8741a/lan8741ai ds00001988a-page 94 ? 2013-2015 microchip technology inc. 5.7 clock circuit the device can accept either a 25 mhz crystal or a 25 mhz single-ended clock oscillator (50ppm) input. if the single- ended clock oscillator method is implemented, xtal2 should be left unconnected and xtal1/clkin should be driven with a nominal 0-3.3 v clock signal. the input clock dut y cycle is 40% minimum, 50% typical and 60% maximum. it is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (xtal1/xtal2). either a 300 w or 100 w 25 mhz crystal may be utilized. the 300 w 25 mhz crystal specifications are detailed in section 5.7.1, "300 w 25 mhz crystal specifications" . the 100 w 25 mhz crystal specifications are detailed in section 5.7.2, "100 w 25 mhz crystal specifications" . 5.7.1 300 w 25 mhz cr ystal specifications when utilizing a 300 w 25 mhz crystal, the following circuit design ( figure 5-8 ) and specifications ( table 5-15 ) are required to ensure proper operation. note 1: the maximum allowable values for frequency tolerance and frequency stability are application dependent. since any particular application must meet the ieee 50 ppm total ppm budge t, the combination of these two values must be approximately 45 ppm (allowing for aging). 2: frequency deviation over time is also referred to as aging. figure 5-8: 300 w 25 mhz crystal circuit table 5-15: 300 w crystal specifications parameter symbol min. nom. max. unit note crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 25.000 - mhz frequency tolerance at 25 o cf tol - - 50 ppm (see note 1 ) frequency stability over temp f temp - - 50 ppm (see note 1 ) frequency deviation over time f age - 3 to 5 - ppm (see note 2 ) total allowable ppm budget - - 50 ppm (see note 3 ) shunt capacitance c o -7 typ-pf load capacitance c l - 20 typ - pf drive level p w 300 - - w equivalent series resistance r 1 --50 ? operating temperature range (see note 4 )- (see note 5 ) o c xtal1/clkin pin capacitance - 3 typ - pf (see note 6 ) xtal2 pin capacitance - 3 typ - pf (see note 6 ) lan8741 xtal2 xtal1 y1 c 1 c 2
? 2013-2015 microchip technology inc. ds00001988a-page 95 lan8741a/lan8741ai 3: the total deviation for the transmitter clock frequency is specified by ieee 802.3u as 50 ppm. 4: 0c for commercial version, -40c for industrial version 5: +70c for commercial version, +85c for industrial version 6: this number includes the pad, the bond wire and the lead frame. pcb capacitance is not included in this value. the xtal1/clkin pin, xtal2 pin and pcb capaci tance values are required to accurately calculate the value of the two external load capacitors. these tw o external load capacitors determine the accuracy of the 25.000 mhz frequency. 5.7.2 100 w 25 mhz cr ystal specifications when utilizing a 100 w 25 mhz crystal, the following circuit design ( figure 5-9 ) and specifications ( table 5-16 ) are required to ensure proper operation. figure 5-9: 100 w 25 mhz crystal circuit table 5-16: 100 w crystal specifications parameter symbol min. nom. max. unit note crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 25.000 - mhz frequency tolerance at 25 o cf tol - - 50 ppm (see note 1 ) frequency stability over temp f temp - - 50 ppm (see note 1 ) frequency deviation over time f age - 3 to 5 - ppm (see note 2 ) total allowable ppm budget - - 50 ppm (see note 3 ) shunt capacitance c o --5pf load capacitance c l 8- 12pf drive level p w - 100 - w (see note 4 ) equivalent series resistance r 1 --80 ? xtal2 series resistor r s 495 500 505 ohm operating temperature range (see note 5 )- (see note 6 ) o c xtal1/clkin pin capacitance - 3 typ - pf (see note 7 ) xtal2 pin capacitance - 3 typ - pf (see note 7 ) lan8741 xtal2 xtal1 r s y1 c 1 c 2
lan8741a/lan8741ai ds00001988a-page 96 ? 2013-2015 microchip technology inc. note 1: the maximum allowable values for frequency tolerance and frequency stability are application dependent. since any particular application must meet the ieee 50 ppm total ppm budge t, the combination of these two values must be approximately 45 ppm (allowing for aging). 2: frequency deviation over time is also referred to as aging. 3: the total deviation for the transmitter clock frequency is specified by ieee 802.3u as 50 ppm. 4: the crystal must support 100 w operation to utilize this circuit. 5: 0c for commercial version, -40c for industrial version 6: +70c for commercial version, +85c for industrial version 7: this number includes the pad, the bond wire and the lead frame. pcb capacitance is not included in this value. the xtal1/clkin pin, xtal2 pin and pcb capaci tance values are required to accurately calculate the value of the two external load capacitors (c 1 and c 2 in figure 5-9 ). the external load capacitors, c 1 and c 2 , determine the accuracy of the 25.000 mhz frequency.
? 2013-2015 microchip technology inc. ds00001988a-page 97 lan8741a/lan8741ai 6.0 package outline b a 0.20 c 0.20 c 0.10 c a b 0.05 c (datum b) (datum a) c seating plane note 1 1 2 n 2x top view side view bottom view for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: note 1 1 2 n 0.10 c a b 0.10 c a b 0.10 c 0.08 c microchip technology drawing c04-160b sqfn sheet 1 of 2 32-lead very thin plastic quad flat, no lead package (mq) - 5x5x0.9 mm body [vqfn] 2x 32x d e 32x b e 2 e 32x l a a1 (a3) d2 e2 32x k smsc legacy sqfn
lan8741a/lan8741ai ds00001988a-page 98 ? 2013-2015 microchip technology inc. microchip technology drawing c04-160b sqfn sheet 2 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: number of terminals overall height terminal width overall width overall length terminal length exposed pad width exposed pad length terminal thickness pitch standoff units dimension limits a1 a b d e2 d2 a3 e l e n 0.50 bsc 0.20 ref 3.20 0.35 0.18 0.80 0.00 0.25 5.00 bsc 0.40 3.30 0.90 0.02 5.00 bsc millimeters min nom 32 3.40 0.45 0.30 1.00 0.05 max k- 0.20 - ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1. 2. 3. notes: pin 1 visual index feature may vary, but must be located within the hatched area. package is saw singulated dimensioning and tolerancing per asme y14.5m terminal-to-exposed-pad 32-lead very thin plastic quad flat, no lead package (mq) - 5x5x0.9 mm body [vqfn] smsc legacy sqfn 3.20 3.30 3.40
? 2013-2015 microchip technology inc. ds00001988a-page 99 lan8741a/lan8741ai recommended land pattern dimension limits units c2 optional center pad width contact pad spacing optional center pad length contact pitch y2 x2 3.40 3.40 millimeters 0.50 bsc min e max 4.90 contact pad length (x32) contact pad width (x32) y1 x1 0.85 0.30 microchip technology drawing c04-2160c sqfn nom 32-lead very thin plastic quad flat, no lead package (mq) - 5x5mm body [vqfn] silk screen c1 contact pad spacing 4.90 contact pad to center pad (x32) g1 0.33 thermal via diameter v thermal via pitch ev 0.33 1.20 bsc: basic dimension. theoretically exact value shown without tolerances. notes: dimensioning and tolerancing per asme y14.5m for best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process 1. 2. for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: smsc legacy sqfn contact pad to contactr pad (x28) g2 0.20 1 2 32 c1 c2 ev ev x2 y2 e x1 y1 g1 g2 ?v
lan8741a/lan8741ai ds00001988a-page 100 ? 2013-2015 microchip technology inc. appendix a: revision history revision level & date section/figure/entry correction revision a (09-07-15) replaces the previous smsc version rev. 1.1 ? added note and trademark page ? added worldwide sales and services page ? added product identification system ? changed ?qfn? to ?vqfn? chapter 2, "pin description and configuration" ? figure 2-1 : rotated 90 cw ? table 2-3, ?serial management interface (smi) pins? : changed ?vis/vod8 (pu)? to ?vis/vo8 (pu)? section 4.1, "register nomenclature" table 4-1, ?register bit types? , register bit description for byte type notification ?w?: changed ?read? to ?written? section 5.6.4, "rmii interface timing" updated rmii timing table: updated ref_clk in mode t oval max from ?14.0 ns? to ?15.0 ns? section 5.7, "clock circuit" added new 100 w crystal specifications and circuit diagram. the section is now split into two subsections, one for 300 w crystals and the other for 100 w crystals. chapter 6, "package outline" updated package outline drawing information rev. 1.1 (05-21-13) general ? changed part numbers from ?lan8741/lan8741i? to ?lan8741a/lan8741ai? ? updated ordering information ? updated figures cover added new bullet under highlights section: ?deterministic 100 mb internal loopback latency (mii mode)? chapter 2, "pin description and configuration" , table 2-1, ?mii/rmii signals? changed buffer type from ?vis (pu)? to ?vis? chapter 2, "pin description and configuration" , table 2-3, ?serial management interface (smi) pins? ? added pull-up to mdio buffer type description ? changed ?vis/vod8 (pu)? to ?vis/vo8 (pu)? section 3.3, "hp auto-mdix support" changed ?100base-t? to ?100base-tx? section 3.4.2.1, "crs_dv - carrier sense/receive data valid" changed ?100base-x? to ?100base-tx? section 3.5, "serial management interface (smi)" removed sentence stating ?non-supported registers (such as 7 to 15) will be read as hexadecimal ?ffff?. section 3.8.10.1, "near-end loopback" added cross-reference to 100 mbps internal loopback timing section section 4.2.2, "basic status register" updated definitions of bits 10:8 section 4.2.16, "special control/status indications register" updated bit 11 definition section 4.2.19, "phy special control/status register" updated bit 6 definition section 4.3, "mdio manageable device (mmd) registers" added additional vendor specific mmd register descriptions chapter 5, "operational characteristics" removed section ?power sequence timing?
? 2013-2015 microchip technology inc. ds00001988a-page 101 lan8741a/lan8741ai rev. 1.1 (05-21-13) section 5.1, "absolute maximum ratings*" changed: positive voltage on xtal1/clkin, with respect to ground from ?vddcr? to ?+3.6v? section 5.3 , table 5-1, ?package thermal parameters? updated package thermal specification values section 5.4, "power consumption" updated power numbers section 5.5, "dc specifications" changed v ihi max of iclk type buffer from ?vddcr? to ?3.6? section 5.6, "ac specifications" removed two rmii notes at beginning of section section 5.6.3.1, "100 mbps internal loopback mii timing" added new 100 mbps internal loopback timing section and diagram section 5.6.4, "rmii interface timing" ? added note detailing crs_dv behavior as both carrier sense and data valid ? updated rmii timing table rev. 1.0 (05-11-12) initial release revision level & date section/figure/entry correction
lan8741a/lan8741ai ds00001988a-page 102 ? 2013-2015 microchip technology inc. notes:
? 2013-2015 microchip technology inc. ds00001988a-page 103 lan8741a/lan8741ai the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification servic e helps keep customers current on microc hip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://microchip.com/support
lan8741a/lan8741ai ds00001988a-page 104 ? 2013-2015 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: lan8741a temperature range: blank = 0c to +70c i = -40c to +85c package: en = vqfn (32-pin) tape and reel option: blank = standard packaging (tray) tr = tape and reel (1) examples: a) LAN8741A-EN 0c to +70c, (32-pin), tray b) lan8741ai-en -40c to +85c, (32-pin), tray c) LAN8741A-EN-tr 0c to +70c, (32-pin), tape and reel note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the dev ice package. check with your microchip sale s office for package availability with the tape and reel option. reel size is 5,000. part no. device [x] temperature range xx package [xx] (1) tape and reel option
? 2013-2015 microchip technology inc. ds00001988a-page 105 information contained in this publication regarding device appli cations and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with yo ur specifications. microchip make s no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liabilit y arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entirely at the buyer? s risk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, claims, suits, or ex penses resulting from such use. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo , dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technolog y incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered tr ademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generati on, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademark of microchi p technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., i n other countries. all other trademarks mentioned herein are property of their respective companies. ? 2013-2015, microchip technology incorporated, pr inted in the u.s.a., all rights reserved. isbn: 978-1-63277-637-2 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner out side the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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